A pcb board and device compatible with different bit width ddr
A PCB board, double-speed synchronization technology, applied in the field of PCB boards and devices, can solve the problems of low cost performance, poor compatibility, and low PCB board reusability, and achieve the goals of reducing costs, improving reusability and compatibility Effect
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Embodiment 1
[0075] refer to Figure 4 , in the 32bit DDR memory controller compatible with 8bit / 16bit DDR3PCB board, among them, the first type of DDR is DDR3 with 16bit bit width, and the second type of DDR is DDR3 with 8bit bit width,
[0076] The address command line is connected to the address command pin of the main control chip and each address command pad (ie CAsignal) in the PCB board;
[0077] The first data line group is connected to a first-type data pin (that is, data pins corresponding to Byte1 and Byte2) in the main control chip and a group of basic data blocks in a first-type DDR (16bit wide DDR3). point(Byte1 in Location1, Byte2 in Location2);
[0078] The second data line group is used to connect a second type of data pin (data pins corresponding to Byte0 and Byte3) in the main control chip and a group of basic data blocks in a second type of DDR (DDR3 with a bit width of 8 bits) Solder joints and a group of basic data block solder joints (Byte0 in Location1, Byte3 in L...
Embodiment 2
[0081] refer to Figure 5 , in a 32bit DDR memory controller compatible with 8bit / 16bit DDR3PCB boards, the first type of DDR is DDR3 with 16bit width, and the second type of DDR is also DDR3 with 16bit width.
[0082] The address command line is connected to the address command pin of the main control chip and each address command pad (ie CAsignal) in the PCB board;
[0083] The first data line group is connected to a first-type data pin in the main control chip (that is, data pins corresponding to Byte0 and Byte3) and a group of basic data blocks in a first-type DDR (DDR3 with a 16-bit bit width). Point(Byte0 in Location1, Byte3 in Location2);
[0084] The second data line group is used to connect a second type of data pin (data pins corresponding to Byte1 and Byte2) in the main control chip with a group of basic data blocks in a second type of DDR (16bit wide DDR3) The solder joints and a group of basic data block solder joints (Byte1 in Location1, Byte2 in Location2) in ...
Embodiment 3
[0089] refer to Figure 6 , in the 32bit DDR memory controller compatible with 16bit / 32bit DDR3PCB board, the first type of DDR is DDR3 with 32bit width, and the second type of DDR is DDR3 with 16bit width.
[0090] The address command line is connected to the address command pin of the main control chip and each address command pad (ie CAsignal) in the PCB board;
[0091] Since the second type of DDR is 16bit wide DDR3, therefore,
[0092]The second data line group connects a second type of data pin (data pins corresponding to Byte0 and Byte2) in the main control chip and a group of basic data block solder joints in a second type of DDR (16bit wide DDR3) (Byte0 in Location0, Byte2 in Location2) and a group of basic data block solder joints (Byte0, Byte2 in Location1) that are not connected to the first data line group in the first type of DDR;
[0093] The first data line group is connected to a first-type data pin in the main control chip (that is, the data pins correspond...
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