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Fault detection method and apparatus

A fault detection and to-be-detected technology, applied in the field of communications, can solve problems such as detection lines, inability to use walking methods, etc., to achieve the effect of reducing fault detection time and high fault location accuracy

Active Publication Date: 2016-05-18
XINHUASAN INFORMATION TECH CO LTD
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Problems solved by technology

[0005] For application scenarios where the address to be detected is not a physical address that the CPU can handle, the CPU cannot use the walking method to detect whether there are faults such as short circuits, open circuits, and fixed logic.

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  • Fault detection method and apparatus

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Embodiment Construction

[0034] In order to improve memory access bandwidth, continuous physical address blocks are usually allocated alternately to different Ranks. This allocation process is called interleaving. Rank refers to a group of DRAM (Dynamic Random Access Memory, dynamic random access memory) chips that are connected to gate lines of the same chip and can operate synchronously. The data bit width of one Rank can be 64 bits. When consecutive physical address blocks are allocated to different Ranks alternately, there are three types of addresses. 1. System physical address, that is, the physical address that the CPU can handle; 2. Memory channel address, that is, the address in the memory channel (Channel) of the CPU; 3. Physical Rank address, that is, the address on a single Rank of the memory.

[0035] In the above application scenarios, the address that needs to be detected by the walking method is the physical Rank address, and the address that the CPU can perform write and read operatio...

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Abstract

The invention provides a fault detection method and apparatus. The method comprises the steps of obtaining a physical Rank address corresponding to Rank where a to-be-detected circuit is; converting the physical Rank address into a system physical address; writing data into the system physical address and reading the data from the system physical address; and by utilizing the data written in the system physical address and the data read from the system physical address, determining whether the to-be-detected circuit has a fault or not. Through the technical scheme provided by the invention, a central processor can detect whether faults such as a short circuit, an open circuit, fixed logic and the like exist or not by adopting a walking method, higher fault positioning precision is provided, and the fault detection time is shortened.

Description

technical field [0001] The present invention relates to the field of communication technology, in particular to a fault detection method and device. Background technique [0002] The CPU (Central Processing Unit, central processing unit) and the memory (that is, memory sticks or memory particles) are connected through lines (that is, data lines or address lines), and there may be three types of faults in the lines used to connect the CPU and memory. The two kinds of faults are: 1. Short circuit: the pins of the two lines are shorted together so that the levels of the two lines are the same. If the final level is dominated by the high level, this type of short circuit is called 1 dominant type Short circuit, if the final level is dominated by low level, this type of short circuit is called 0 dominated short circuit. 2. Open circuit: some pins with lines are open circuited. 3. Fixed logic: Some pins with lines are fixedly pulled to a fixed level, such as shorted to ground. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22
Inventor 刘晓军
Owner XINHUASAN INFORMATION TECH CO LTD
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