Two-dimensional discrete wavelet transform realization method based on coarse granularity reconfigurable system

Abstract

The invention provides a two-dimensional discrete wavelet transform realization method based on a coarse granularity reconfigurable system. The method comprises following steps: dividing a two-dimensional discrete wavelet transform algorithm into a row transform algorithm and a column transform algorithm; transforming the row transform algorithm and the column transform algorithm into parallelized data control flow diagrams; determining a data input output mode and a data organization structure; mapping the parallelized data control flow diagrams to different processing unit arrays; caching the intermediate result data of the row transform and column transform through a shared memory, thus realizing the two-dimensional discrete wavelet transform algorithm. In adoption of the reconfigurable system technique to realize the two-dimensional discrete wavelet transform algorithm, balance of high efficiency and flexibility is realized; the data calculation performance demand of the two-dimensional discrete wavelet transform can be satisfied; the wavelet basis and length can be adjusted according to the demand; the method is beneficial for further developing and upgrading the algorithm; and the discrete wavelet transform algorithm realized by using the reconfigurable system technique has both flexibility and high performance..

Description

technical field [0001] The invention belongs to the technical field of coarse-grained reconfigurable systems, and in particular relates to a coarse-grained reconfigurable system applicable to image compression, signal processing and other occasions and a processing method thereof. Background technique [0002] In the mainstream computing model, processors and application-specific integrated circuits (ASICs) have always been the two mainstreams. With the continuous improvement of application fields, especially embedded environments, for system performance, energy consumption, time-to-market and other indicators, traditional computing models have exposed various drawbacks. [0003] The processor method can flexibly implement various applications, but it has defects in performance; while the hardware logic implementation has high performance, but its flexibility is poor. In order to make a good trade-off between computing performance and implementation flexibility, reconfigura...

AI Technical Summary

Problems solved by technology

The existing two-dimensional discrete wavelet transform algorithm has the characteristics of large amount of data calculation and high degree of algorithm flexibility. It is difficult for ASIC implementation to meet the requirements of the two-dimensional discrete wavelet transform algorithm with multiple lengths and multiple wavelet bases, and general calculation is difficult. Meet the performance requirements of two-dimensional discrete wavelet transform for massive data calculation

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