Unlock instant, AI-driven research and patent intelligence for your innovation.

Circuit and method for equalizing impedance of pmos device and nmos device

A circuit and equalization technology, applied in logic circuits, electrical components, electrical signal transmission systems, etc., can solve problems such as errors and different voltages

Active Publication Date: 2021-01-01
TEXAS INSTR INC
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

NMOS and PMOS devices have different impedances, which cause capacitors to drain at different rates
The result is that different voltages appear across the capacitors during the voltage decay, which causes errors when comparing the voltages across the capacitors

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Circuit and method for equalizing impedance of pmos device and nmos device
  • Circuit and method for equalizing impedance of pmos device and nmos device
  • Circuit and method for equalizing impedance of pmos device and nmos device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] Circuits and methods for equalizing the impedance of PMOS and NMOS devices are described herein with reference to a successive approximation register (SAR) integrated with a digital-to-analog converter (DAC). figure 1 is a block diagram of one embodiment of a SAR loop 100 integrated with a DAC 102 . In addition to DAC 102 , SAR loop 100 includes comparator 104 and SAR control circuit 106 . DAC 102 has an input voltage V that is coupled or capable of being coupled to a digital signal to be converted IN The input 110. In some aspects of the SAR loop 100, the DAC 102 also has the capability of being coupled or capable of being coupled to a reference voltage V REF The input 112. In some aspects, the reference voltage V REF . DAC 102 is sometimes referred to as a capacitive DAC or C-DAC.

[0020] In summary, the comparator 104 takes the input voltage V IN It is compared with the voltage selected by the SAR control circuit 106 . In some versions of SAR loop 100, compa...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A circuit (400) for equalizing impedance of a PMOS device and an NMOS device includes a first reference voltage REFP coupled to a source of a first PMOS device. A second reference voltage REFM is coupled to the source of the NMOS device. The first node N1 has a common mode voltage between the first reference voltage REFP and the second reference voltage REFM. The second node N2 is located between the PMOS device and the NMOS device. The first gate voltage is coupled to the gate of either the PMOS device or the NMOS device. An operational amplifier (402) has a first input coupled to a first node N1 and a second input coupled to a second node N2, the output of the operational amplifier (402) is coupled to either a PMOS device or an NMOS device, The second gate voltage V3 is not coupled to the gate of the first gate voltage.

Description

technical field Background technique [0001] Some analog-to-digital converters (ADCs) have a successive approximation register (SAR) topology. These converters work by comparing an analog voltage signal to a known portion of the full-scale input voltage and then setting or clearing a bit in the ADC data register. Some SAR converters use a capacitive digital-to-analog converter (C-DAC) to compare bit patterns successively. For example, the first bit is based on half-scale input voltage compared to the input voltage. In response to the first comparison, the second bit is based on a comparison of one quarter or three quarters of the full scale input voltage. [0002] Charge kickback occurs when the comparator is released from the reset condition, and a determination will be made as to whether the voltage at the inverting input or the non-inverting input is greater. Immediately after the comparator is released from reset and depending on the speed of the comparator, it flushes...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/38H03M1/66
CPCH03M1/468H03K19/0944H03K19/018514
Inventor S·保罗
Owner TEXAS INSTR INC