Memory compiler timing sequence simulation method

Abstract

The present invention relates to the technical field of memory timing sequence simulation, and especially relates to a memory compiler timing sequence simulation method. A timing sequence path is divided, each subpath set is only individually related to one parameter, timing sequence simulation is carried out on each subpath set about the parameter individually related to each subpath set, then simulation results are calculated through a mathematical model to obtain a full path timing sequence of the timing sequence, so that the accurate simulation results are obtained, computing resource consumption is effectively reduced, and furthermore, timing sequence simulation efficiency is improved, and simulation cost is also reduced.

Description

technical field [0001] The invention relates to the technical field of memory sequence simulation, in particular to a memory compiler sequence simulation method. Background technique [0002] The large-scale integrated circuit timing simulation under the deep submicron process is very time-consuming and resource-consuming, especially for high-density memory compilers, the timing simulation is aimed at different memory instances (the memory instance is a memory with a specific capacity generated by the memory compiler Macrocell), input ramp (input ramp is the time when the input signal transitions from low to high (or vice versa)) and output load (output load is the gate and wire load driven by the output, etc. The combination of effective capacitors) requires doubling of computing resources, and in many cases, the simulation may fail due to too long timing paths. [0003] The memory instance generated by the memory compiler is an indispensable basic IP (Intellectual Propert...

AI Technical Summary

Problems solved by technology

Although this technique reduces the consumption of computing resources, it has the disadvantage of very imprecise timing

Images