9 results about "Memory timings" patented technology

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

A chiplet-based smart integrated compute system includes a safe compute subsystem and a safe compute and safety monitoring subsystem linked by die-to-die interconnects for high- speed, low-latency, freedom-from-interference operation. Dedicated secondary storage subsystems, clock-generation subsystems (with crystal oscillators), and power-regulation subsystems (with pre-regulators) provide domain-specific memory, timing, and power. A safe smart power management subsystem with a microcontroller manages intelligent distribution, autonomous power-on / reset, over-the-air (OTA) updates to power-management integrated circuits, and selective isolation during faults. The microcontroller monitors thermal / electrical health and can selectively shut down a faulty domain. The safe compute subsystem may serve as a secure communication gateway to external electronic control units via a wireless link on a network, using a cryptographic processing unit with hardware-embedded keys. Diagnostic telemetry is transmitted to a cloud for predictive maintenance and policy refinement.

A device control method, an electronic device and a storage medium, relate to the technical field of terminals. After the electronic device enters a recovery mode, memory repair processing is sequentially performed until the internal memory supports the electronic device to successfully boot up; wherein each time the memory repair processing includes: controlling the internal memory to enter a test mode; and adjusting a parameter value of a memory timing parameter of the internal memory in the test mode of the internal memory. The internal memory is repaired by a software method, so that the electronic device can be restored to normal booting based on the repaired internal memory without restoring factory settings.

A method for time borrowing in memory timing paths of a memory is described. The method includes holding memory input data in a latch buffer according to a core clock. The method also includes delaying the core clock to generate a memory clock. The method further includes feeding the memory input data from the latch buffer to a memory input of the memory according to the memory clock. The method also includes accessing a memory output of the memory according to the core clock.

The invention discloses a time-sensitive data dynamic slice scheduling method in an edge computing environment, and belongs to the technical field of data processing. The method specifically comprises the following steps: S1, edge node deployment: selecting an edge node deployment position according to a kitchen ware type, configuring edge node hardware, and deploying an edge node software system; s2, multi-source data acquisition: self-adapting to multi-source data acquisition frequency according to the state of the kitchen ware, and automatically switching a data acquisition mode. Edge node deployment is efficient and stable, the basic performance of the system is improved, and lightweight and efficient collaboration of the edge nodes is achieved through customized hardware configuration and software deployment. The memory time sequence calibration and the flash memory partition division of the hardware level guarantee the reasonable distribution of storage resources; and a micro-service starting sequence control and real-time monitoring mechanism at a software level ensures ordered linkage of data acquisition, preprocessing and scheduling services, reduces coupling among the services, and improves the overall stability and response speed of the system.

The application discloses a kind of server memory parameter intelligent optimization method and device, the method is by collecting the characteristic data of service scene;According to the characteristic data, the corresponding target memory time sequence parameter is generated by the preset parameter mapping hybrid model, wherein the parameter mapping hybrid model includes the basic mapping layer for linear mapping and the feature interaction enhancement layer for nonlinear calibration;The target memory time sequence parameter is checked based on the service priority of service scene security, and after passing the security check, the target memory time sequence parameter is configured, the accurate matching of memory time sequence parameter and dynamic service scene is realized, and performance potential can be fully released under the premise of guaranteeing the stability of core business, can significantly improve the intelligent level and overall operation efficiency of business operation system.

A method for time borrowing in memory timing paths of a memory is described. The method includes holding memory input data in a latch buffer according to a core clock. The method also includes delaying the core clock to generate a memory clock. The method further includes feeding the memory input data from the latch buffer to a memory input of the memory according to the memory clock. The method also includes accessing a memory output of the memory according to the core clock.

A chiplet-based smart integrated compute system includes a safe compute subsystem and a safe compute and safety monitoring subsystem linked by die-to-die interconnects for high-speed, low-latency, freedom-from-interference operation. Dedicated secondary storage subsystems, clock-generation subsystems (with crystal oscillators), and power-regulation subsystems (with pre-regulators) provide domain-specific memory, timing, and power. A safe smart power management subsystem with a microcontroller manages intelligent distribution, autonomous power-on / reset, over-the-air (OTA) updates to power-management integrated circuits, and selective isolation during faults. The microcontroller monitors thermal / electrical health and can selectively shut down a faulty domain. The safe compute subsystem may serve as a secure communication gateway to external electronic control units via a wireless link on a network, using a cryptographic processing unit with hardware-embedded keys. Diagnostic telemetry is transmitted to a cloud for predictive maintenance and policy refinement.

The application provides a kind of intelligent chip memory access control method and system based on timing parameter optimization.The method comprises: dividing physical memory into first area and second area, and storing data to be accessed in first area and second area simultaneously, wherein first area is configured with first memory timing parameter for determining memory particle access timing, and second area is configured with second memory timing parameter more aggressive than first memory timing parameter;In response to a data read request, corresponding data to be accessed is read from the second area, and the access error rate of the second area is monitored.When the access error rate exceeds the preset threshold, the corresponding data to be accessed is synchronized from the first area to the second area.Using the application, timing parameter optimization can be performed on part of the memory area while ensuring data reliability, the best performance parameter combination is determined through experiments, system stability is ensured, and memory bus utilization is significantly improved.