37 results about "Memory timings" patented technology

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.

A system and method for thermally coupling memory devices, such as DIMM memory modules, to an associated memory controller such that both are cooled together at the same relative temperature. By maintaining all of the devices at a much more uniform temperature, memory timing issues are effectively eliminated. In accordance with an exemplary embodiment, the controller chip is physically located between two or more banks of memory, and is positioned under an adjoining heat sink while the memory DIMMs are positioned laterally of the controller chip in angled DIMM slots and are coupled to the controller chip with respective heat spreaders.

An apparatus and method is disclosed for providing capacity on demand using control to alter latency and / or bandwidth on a signaling bus in a computer system. If additional capacity is required, authorization is requested for additional capacity. If authorized, bandwidth of the signaling bus is increased to provide additional capacity in the computing system. Alternatively, upon authorization, latency of data transmissions over the signaling bus is reduced. In another alternative, upon authorization, memory timings are adjusted to speed up memory fetches and stores.

This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices.