16 results about "Memory timings" patented technology

In an implementation, a memory subsystem may include input / output (I / O) circuitry having a data signal (DQ) group, the DQ group having multiple DQ lanes and a read data strobe, and one or more controllers coupled to the I / O circuitry, the one or more controllers being configured to assign, respectively to multiple DQ lanes of the DQ group, multiple read test delays that monotonically increase with respect to a read eye edge, read a read test value one time, using the DQ group, with the multiple read test delays respectively for each DQ lane in the DQ group, and update the read eye edge by adding a first read test delay, corresponding to a first DQ lane of the DQ lanes from the read test value that does not match a read eye training pattern, to the read eye edge to calculate a trained read eye edge.

The invention discloses a memory time sequence parameter tuning method and device, computer equipment and a storage medium, relates to the technical field of server memories, and dynamically relates to time sequence parameter combination and memory interface signal quality by establishing an automatic closed-loop process of parameter configuration, signal measurement, condition verification and parameter optimization. Parameter suitability is accurately judged based on an actual measurement result, and a parameter optimization mechanism is driven to automatically iterate to generate a new candidate parameter combination, so that dependence on artificial experience is eliminated, and the limitation that a traditional method is low in efficiency and difficult to deal with dynamic changes in a complex parameter space is overcome. Therefore, the technical problems that in the prior art, memory time sequence parameter tuning is low in efficiency, poor in adaptability and insufficient in stability are solved, and the technical effects of remarkably improving the integrity of memory signals, enhancing the running stability of a server and improving the energy efficiency ratio of a memory subsystem are achieved.

The application discloses a new clock tree adaptive optimization method based on RISC-V architecture and utilizing useful skew, after S1, layout; S2, layout; S3, clock tree synthesis, S10, register-to-register timing path optimization is carried out; after S4, wiring, S20, register-to-memory timing path optimization is carried out. Through adaptive iteration, the application does not need complicated algorithms, solves the shortage of auto useful skew of the EDA tool itself, maximally repairs the timing problem, and simultaneously adopts the method of combining delay units, so that the win-win effect of high performance and low power consumption of chip design is realized.

An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

A chiplet-based smart integrated compute system includes a safe compute subsystem and a safe compute and safety monitoring subsystem linked by die-to-die interconnects for high- speed, low-latency, freedom-from-interference operation. Dedicated secondary storage subsystems, clock-generation subsystems (with crystal oscillators), and power-regulation subsystems (with pre-regulators) provide domain-specific memory, timing, and power. A safe smart power management subsystem with a microcontroller manages intelligent distribution, autonomous power-on / reset, over-the-air (OTA) updates to power-management integrated circuits, and selective isolation during faults. The microcontroller monitors thermal / electrical health and can selectively shut down a faulty domain. The safe compute subsystem may serve as a secure communication gateway to external electronic control units via a wireless link on a network, using a cryptographic processing unit with hardware-embedded keys. Diagnostic telemetry is transmitted to a cloud for predictive maintenance and policy refinement.

A device control method, an electronic device and a storage medium, relate to the technical field of terminals. After the electronic device enters a recovery mode, memory repair processing is sequentially performed until the internal memory supports the electronic device to successfully boot up; wherein each time the memory repair processing includes: controlling the internal memory to enter a test mode; and adjusting a parameter value of a memory timing parameter of the internal memory in the test mode of the internal memory. The internal memory is repaired by a software method, so that the electronic device can be restored to normal booting based on the repaired internal memory without restoring factory settings.

A method for time borrowing in memory timing paths of a memory is described. The method includes holding memory input data in a latch buffer according to a core clock. The method also includes delaying the core clock to generate a memory clock. The method further includes feeding the memory input data from the latch buffer to a memory input of the memory according to the memory clock. The method also includes accessing a memory output of the memory according to the core clock.

This application discloses a method, apparatus, computer device, and storage medium for optimizing memory timing parameters, relating to the field of server memory technology. By establishing an automated closed-loop process of parameter configuration, signal measurement, condition verification, and parameter optimization, it dynamically correlates timing parameter combinations with memory interface signal quality. Based on actual measurement results, it accurately judges parameter suitability and drives a parameter optimization mechanism to automatically iterate and generate new candidate parameter combinations. This eliminates reliance on manual experience and overcomes the limitations of traditional methods, such as low efficiency and difficulty in handling dynamic changes in complex parameter spaces. Therefore, it solves the technical problems of low efficiency, poor suitability, and insufficient stability in existing memory timing parameter optimization technologies, achieving significant improvements in memory signal integrity, enhanced server operational stability, and increased energy efficiency of the memory subsystem.

The invention discloses a time-sensitive data dynamic slice scheduling method in an edge computing environment, and belongs to the technical field of data processing. The method specifically comprises the following steps: S1, edge node deployment: selecting an edge node deployment position according to a kitchen ware type, configuring edge node hardware, and deploying an edge node software system; s2, multi-source data acquisition: self-adapting to multi-source data acquisition frequency according to the state of the kitchen ware, and automatically switching a data acquisition mode. Edge node deployment is efficient and stable, the basic performance of the system is improved, and lightweight and efficient collaboration of the edge nodes is achieved through customized hardware configuration and software deployment. The memory time sequence calibration and the flash memory partition division of the hardware level guarantee the reasonable distribution of storage resources; and a micro-service starting sequence control and real-time monitoring mechanism at a software level ensures ordered linkage of data acquisition, preprocessing and scheduling services, reduces coupling among the services, and improves the overall stability and response speed of the system.

This invention discloses a multi-channel acoustic emission signal acquisition system based on an AD analog-to-digital converter (AD) IP core. The system comprises: an AD IP core that drives multiple channel AD chips to perform analog-to-digital conversion to obtain acoustic emission data, and integrates the acoustic emission data from multiple channels before sending it to a FIFO buffer module; a FIFO buffer module that buffers the integrated acoustic emission data; a DMA module that transmits the integrated acoustic emission data buffered in the FIFO buffer module to the DDR3 memory of a host computer; a timing control module that receives a clock signal generated by the host computer and transmits it to other modules; and a host computer that provides the clock signal required by the multi-channel data acquisition system, retrieves the integrated acoustic emission data from the DDR3 memory, and extracts the acoustic emission data of each channel through bitwise operations. This invention achieves channel partitioning functionality in a multi-channel data acquisition system through multi-channel data integration and bitwise operations, reducing the workload and complexity of system development and design, and increasing the proportion of effective data bits in the transmitted data.

The application discloses a kind of server memory parameter intelligent optimization method and device, the method is by collecting the characteristic data of service scene;According to the characteristic data, the corresponding target memory time sequence parameter is generated by the preset parameter mapping hybrid model, wherein the parameter mapping hybrid model includes the basic mapping layer for linear mapping and the feature interaction enhancement layer for nonlinear calibration;The target memory time sequence parameter is checked based on the service priority of service scene security, and after passing the security check, the target memory time sequence parameter is configured, the accurate matching of memory time sequence parameter and dynamic service scene is realized, and performance potential can be fully released under the premise of guaranteeing the stability of core business, can significantly improve the intelligent level and overall operation efficiency of business operation system.

A method for time borrowing in memory timing paths of a memory is described. The method includes holding memory input data in a latch buffer according to a core clock. The method also includes delaying the core clock to generate a memory clock. The method further includes feeding the memory input data from the latch buffer to a memory input of the memory according to the memory clock. The method also includes accessing a memory output of the memory according to the core clock.

A chiplet-based smart integrated compute system includes a safe compute subsystem and a safe compute and safety monitoring subsystem linked by die-to-die interconnects for high-speed, low-latency, freedom-from-interference operation. Dedicated secondary storage subsystems, clock-generation subsystems (with crystal oscillators), and power-regulation subsystems (with pre-regulators) provide domain-specific memory, timing, and power. A safe smart power management subsystem with a microcontroller manages intelligent distribution, autonomous power-on / reset, over-the-air (OTA) updates to power-management integrated circuits, and selective isolation during faults. The microcontroller monitors thermal / electrical health and can selectively shut down a faulty domain. The safe compute subsystem may serve as a secure communication gateway to external electronic control units via a wireless link on a network, using a cryptographic processing unit with hardware-embedded keys. Diagnostic telemetry is transmitted to a cloud for predictive maintenance and policy refinement.

The memory margin test method, system and device and the medium provided by the embodiment of the invention comprise the steps that a main control module generates a test script in response to a received memory time sequence parameter set by a target object and a selected test option; in response to the received test request sent by the system-level test equipment, the main control module sends a test script to the system-level test equipment; the system-level test equipment receives the test script sent by the main control module and executes the test script so as to test a target memory bank set by the system-level test equipment through the test script; and the main control module captures the Bios log in the process of testing the target memory bank by the system-level test equipment, and determines a memory margin test result of the target memory bank set by the system-level test equipment according to the Bios log. Full-process automation of RMT testing is achieved, manual intervention is reduced, and the testing efficiency and the accuracy of memory stability evaluation are improved.

The application discloses a design method of a multi-core SoC shared external memory interface, wherein a global control register, a clock configuration register and a space control register are internally designed and configured in an external memory interface controller, clock configuration of the external memory interface controller, frequency division coefficient when a system clock is selected, and external memory timing control are performed, the global control register is used for configuring internal working clock of the external memory interface controller and reading external memory state, the clock configuration register is used for configuring output clock of the external memory interface controller and connecting working clock of the external memory, and the space control register is used for external memory read-write timing control of four memory spaces supported by the external memory interface controller; the application optimizes external memory interfaces of multiple processor cores by adopting simplified design, shares one external memory interface, and achieves the effect of reducing system size and improving work efficiency.

The application provides a kind of intelligent chip memory access control method and system based on timing parameter optimization.The method comprises: dividing physical memory into first area and second area, and storing data to be accessed in first area and second area simultaneously, wherein first area is configured with first memory timing parameter for determining memory particle access timing, and second area is configured with second memory timing parameter more aggressive than first memory timing parameter;In response to a data read request, corresponding data to be accessed is read from the second area, and the access error rate of the second area is monitored.When the access error rate exceeds the preset threshold, the corresponding data to be accessed is synchronized from the first area to the second area.Using the application, timing parameter optimization can be performed on part of the memory area while ensuring data reliability, the best performance parameter combination is determined through experiments, system stability is ensured, and memory bus utilization is significantly improved.