DDR packaging structure used for in-pair welding and in-pair welding method of DDR packaging structure

Abstract

The invention discloses a DDR (Double Data Rate) packaging structure used for in-pair welding and an in-pair welding method of the DDR packaging structure. The top face of the packaging substrate of the DDR packaging structure is provided with a first storage control module and a second storage control module while the bottom face is provided with a first pin area and a second pin area. Signal pins of the first storage control module is arranged in the first pin area and signal pins of the second storage control module are arranged in the second pin area. An arbitrary signal pin in the first pin area is in axial symmetry with a signal pin having the same function in the second pin area. The in-pair welding method includes steps of welding the DDR packaging structure on the top layer or the bottom layer of a PCB and welding the DDR packaging structure rotated 180 degrees at the same position on the other side, so that the signal pins having the same functions are overlapped with each other after the in-pair welding. The method can be used for DDC packaging of in-pair welding, and for simplifying a PCB design, saving wiring space and optimizing the signal integrality of DDR high speed signals.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a DDR packaging structure for butt welding and a butt welding method thereof. Background technique [0002] Almost every electronic device, from small wearable devices to large supercomputers, uses RAM memory in some form. DDR (Double Data Rate) is a double data rate SDRAM memory, which has become the choice of memory technology today. DDR technology continues to evolve, increasing speed and capacity while reducing cost, power, and the physical size of storage devices. Chip packaging provides a total bridge between the chip and the PCB board, and has become an important part of electronic components. DDR high-speed signal transmission rate is high, which provides a great challenge to the package substrate design. In order to increase the storage capacity of the single board and save the area of ​​the single board, no matter whether the DIMM strip or the on-board DDR design...

AI Technical Summary

Problems solved by technology

At present, the signal pin arrangement of packaged DDR particles on the market adopts an asymmetrical design. After complete welding and mounting, the network names of the signal pins corresponding to the TOP layer (top layer) and BOTTOM layer (bottom layer) will be inconsistent, and the network names will be the same. The pins are just staggered left and right, which increases the difficulty of fan-out routing on the surface layer and affects signal integrity

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