A ddr packaging structure for butt-welding and a butt-welding method thereof

Abstract

The invention discloses a DDR packaging structure for butt welding and a butt welding method thereof. A first storage control module and a second storage control module are arranged on the top surface of the packaging substrate of the DDR packaging structure, and a second storage control module is arranged on the bottom surface. A first pin area and a second pin area are provided, the signal pins of the first storage control module are arranged in the first pin area, and the signal pins of the second storage control module are arranged in the second pin area , any signal pin in the first pin area and the signal pins with the same function in the second pin area are arranged axially symmetrically; the steps of the mounting method include: first soldering the DDR package structure on the top or bottom layer of the PCB , and then solder and rotate the DDR package structure by 180° at the same position on the other side, so that the same function signal pins overlap with each other after soldering. The invention can be used for packaging the DDR mounted by soldering, simplifies the PCB design, saves layout and wiring space, and optimizes the signal integrity of the DDR high-speed signal.

Description

technical field [0001] The invention relates to semiconductor packaging technology, in particular to a DDR packaging structure for butt welding and a butt welding method thereof. Background technique [0002] Almost every electronic device, from small wearable devices to large supercomputers, uses RAM memory in some form. DDR (Double Data Rate) is a double data rate SDRAM memory, which has become the choice of memory technology today. DDR technology continues to evolve, increasing speed and capacity while reducing cost, power, and the physical size of storage devices. Chip packaging provides a total bridge between the chip and the PCB board, and has become an important part of electronic components. DDR high-speed signal transmission rate is high, which provides a great challenge to the package substrate design. In order to increase the storage capacity of the single board and save the area of ​​the single board, no matter whether the DIMM strip or the on-board DDR design...

AI Technical Summary

Problems solved by technology

At present, the signal pin arrangement of packaged DDR particles on the market adopts an asymmetrical design. After complete welding and mounting, the network names of the signal pins corresponding to the TOP layer (top layer) and BOTTOM layer (bottom layer) will be inconsistent, and the network names will be the same. The pins are just staggered left and right, which increases the difficulty of fan-out routing on the surface layer and affects signal integrity

Images