Communication Method of 3D Optical Chip Network

Abstract

The invention discloses a communication method for a three-dimensional optical on-chip network, which mainly solves the problems of low utilization rate of communication links, single node blocking affecting other node communications, large communication delay and low network throughput in the existing three-dimensional optical on-chip network. The technical solution is: taking the three-dimensional Mesh and Torus structure as an example, when a resource reservation group is blocked at an intermediate node, the resource reservation group is retransmitted according to the real-time network situation, and the resource reservation group is retransmitted during the resource reservation group retransmission process. The conditions for reserving packet retransmission are optimized. The present invention overcomes the problem that the communication blockage in the three-dimensional Mesh and three-dimensional Torus structure is relatively large, and the blockage of a single node affects the communication of other nodes. The lock improves the utilization rate and throughput of the communication link and reduces the delay with little increase in energy consumption, and can be used to realize efficient communication between IP cores on the optical chip.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to a communication method of an on-chip network, which can be used to realize efficient communication between IP cores on an optical chip. Background technique [0002] In the process of system-on-chip developing towards multi-core and heterogeneity, the concept of network-on-chip was proposed. Its core idea is to integrate computer network technology into chip design and completely improve the bus structure from the system structure. series of questions. However, as the number of IP cores on a monolithic integrated circuit reaches many cores or even thousands of cores, and the size of integrated circuits enters the nanometer era, the clock frequency is getting higher and higher, and problems such as parasitic capacitance and signal crosstalk in electrical interconnection technology will become very significant. . Due to the advantages of high bandwidth, low powe...

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Problems solved by technology

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art, and propose a communication method for a three-dimensional optical-on-chip network to remove deadlocks in communication, solve the problem of single node blocking affecting communication of other nodes, improve resource utilization, reduce Delay, improve network throughput

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