Opportunistic Multithreading in Multithreaded Processors with Instruction Chaining Capability

A processor and instruction technology, applied in the field of multi-thread processing of microprocessors, can solve problems such as performance degradation, instruction memory cannot be shared by hardware threads, and memory resources are not fully utilized.

Active Publication Date: 2019-10-18
OPTIMUM SEMICON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, individual instruction memories cannot be shared between hardware threads
When the number of software threads is less than the number of hardware threads, this can lead to underutilization of memory resources in addition to performance degradation

Method used

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  • Opportunistic Multithreading in Multithreaded Processors with Instruction Chaining Capability
  • Opportunistic Multithreading in Multithreaded Processors with Instruction Chaining Capability
  • Opportunistic Multithreading in Multithreaded Processors with Instruction Chaining Capability

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Embodiment Construction

[0036] Examples of the present disclosure describe a multithreaded computer processor and method of operating the multithreaded computer processor that minimizes unused clocks in the multithreaded processor when there are fewer software threads than hardware thread units cycle. Unused clock cycles may occur when an allocated hardware thread unit must issue a NOP. Examples of the present disclosure provide methods and multithreading that can issue awaited instructions to multiple hardware thread units without requiring all preceding hardware thread units to issue NOPs first as in the case of token-triggered multithreading computer processor. An approach known as "opportunistic multithreading" controls instruction issue sequences by providing a two-dimensional array of identification registers associating software threads with several hardware thread units. In each pipeline stage, a thread identifier (ID) may be used to identify the software thread from which the instruction w...

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Abstract

The computing device determines that a current software thread of the plurality of software threads having an issue sequence is not waiting for a first instruction to be issued to a hardware thread during one clock cycle. The computing device identifies one or more alternate software threads in the issue sequence that have instructions waiting to be issued. The computing device selects, during the clock cycle, the second instruction from a second software thread among the one or more alternate software threads having no dependencies on any other instruction among the instructions waiting to be issued. Second instruction. Dependencies are identified in terms of the value of the link bit extracted from each instruction waiting to be issued. The computing device issues a second instruction to a hardware thread.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to U.S. Utility Patent Application No. 14 / 539,116, filed November 12, 2014, which claims U.S. Provisional Patent Application 61 / 936,428, filed February 6, 2014, and 2014 Priority to U.S. Provisional Patent Application No. 61 / 969,862, filed March 25, the entire disclosures of which are incorporated herein by reference. technical field [0003] Embodiments of the present disclosure relate to a method and apparatus for processing instructions in a microprocessor environment. More specifically, embodiments relate to multithreading for microprocessors, that is, when the microprocessor determines that a target hardware thread is empty or has no valid instructions to issue during a particular clock cycle, the microprocessor may Instructions that are assigned to other hardware threads are issued during a clock cycle. Background technique [0004] Multi-thread parallel processing technology ha...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/3851G06F9/3853G06F9/3818G06F9/382G06F9/3822G06F9/3838G06F9/3826G06F9/46
Inventor 王生洪C·J·格洛斯纳G·J·奈塞
Owner OPTIMUM SEMICON TECH
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