An optimization method for resistive variable memory with crossbar structure

Abstract

The invention discloses an optimization method for a resistive variable memory with a crossbar structure, and belongs to the technical field of computer storage. The method of the present invention designs voltage sources at the four terminals of each crossbar array, alleviates the problem of voltage drop on word lines and bit lines at the same time, divides the array into three types of fast, medium, and slow blocks, and maps thermal data to Fast blocks, map warm data to medium blocks, map cold data to slow blocks, and also explore the relationship between block types, RESET delays, and the proportion of low-resistance cells on selected word lines, and map the most appropriate RESET The delay is exposed to the memory controller call, dynamically accelerates the RESET operation, and a solution combining circuit and architecture is designed to solve the problem of read and write interference, thereby optimizing the performance and reliability of ReRAM.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and more particularly relates to an optimization method of a crossbar structure resistive memory. Background technique [0002] The scalability of DRAM is fundamentally limited by its use of capacitors to store data, and it is difficult to shrink further after its process is reduced to 16 nanometers. In addition, DRAM is a kind of volatile memory, and its refresh operation brings huge energy consumption overhead. These challenges with DRAM make it difficult to meet the high-capacity memory demands of today's data-intensive applications. Recently, emerging non-volatile memories (Non-Volatile Memory, NVM) such as Phase Change Memory (Phase Change Memory, PCM), spin-transfer torque random memory (Spin-Transfer Torque Magnetic RAM, STT-MRAM), resistive memory (Resistive Random Access Memory, ReRAM) is actively explored as Storage Class Memory (SCM) due to its high scalability, high storage...

AI Technical Summary

Problems solved by technology

During the read operation, all cells on the selected word line have a voltage of Vread at both ends, and the resistance value of these cells will also change. As the resistance changes accumulate, the resistance state of these cells will also be changed. As a result, data corruption is caused, which is the problem of read interference.

All in all, since there is no access transistor in the crossbar structure to completely isolate the target cell, read and write disturbances cause serious data reliability problems

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