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Power consumption and temperature oriented dynamic and static combined NoC (Network-on-Chip) mapping method

A mapping method and combined technology, applied in the field of network communication, can solve problems such as power consumption increase, weakening NoC advantages, and chip performance impact

Active Publication Date: 2016-11-23
黄山市开发投资集团有限公司
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Problems solved by technology

[0002] Although the change of network-on-chip (NoC) replacing the traditional bus structure overcomes various problems caused by the traditional structure to a certain extent, with the increase of IP (Intellectual Property) cores and the increase of communication traffic, the The power consumption of the interconnection network has become the focus of NoC design. With the reduction of the chip size and the improvement of the overall performance, the power consumption per unit area also increases. This makes the task mapped to the resource node for processing. Rapidly rising, even leading to the generation of local hot spots (Hot Spot); high temperature affects the performance of the chip and may even damage the device, which greatly weakens the advantages of NoC and directly affects the performance of the network system on chip
[0003] NoC mapping is divided into static mapping and dynamic mapping. Static mapping is an offline mapping method. Before the NoC system works, the mapping scheme is obtained through the mapping algorithm, which does not occupy online resources. However, static mapping cannot be adjusted according to the status of the NoC system. The solution optimizes system performance, and the optimization time is long
[0004] Dynamic mapping is an online mapping method. When the NoC system is working, the system working status is obtained, the mapping algorithm is run according to the system status, and the mapping scheme is replaced online. Although the optimization time is fast, dynamic mapping requires a lot of online resources and may not be able to get the optimal solution
[0005] Most of the existing mapping schemes are researches on the choice of one of the two. Optimizing one aspect may degrade the performance of the other, and the traditional NoC mapping algorithm has a single optimization goal, while the optimization goal of most mapping algorithms mainly focuses on communication loss. In terms of performance, such as power consumption and delay, less attention has been paid to the influence of temperature on the mapping system. At the same time, the calculation of node temperature is mainly based on the temperature model tool Hot spot. There is no more effective and direct method to calculate the temperature of each node of the network on chip; For example, the Chinese invention patent CN104079439A "An On-Chip Network Mapping Method Based on Discrete Firefly Algorithm" published on October 1, 2014 improves the traditional firefly algorithm to solve the on-chip network mapping problem, and can quickly and effectively find the optimal mapping solution
The disadvantage of this method is that the mapping optimization target is concentrated on the total communication loss, which may cause the task mapping to be concentrated while reducing the overall communication loss, resulting in higher local node temperature, resulting in hot spots

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  • Power consumption and temperature oriented dynamic and static combined NoC (Network-on-Chip) mapping method

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Embodiment Construction

[0059] In this embodiment, the NoC is an on-chip network composed of communication nodes and computing nodes, and the mapping is to map each task on the application feature map to the computing nodes of the NoC; it is assumed that there are N=X×Y×Z communication nodes in the network on chip , the serial number of the communication node is 0,1,...,k,...,N-1, where k represents the serial number of the kth communication node, 0≤k≤N-1, X represents the number of rows of NoC, and Y represents the number of NoC The number of columns, Z represents the number of layers of NoC, such as figure 1 The shown 4×4×1 network on chip has 16 communication nodes in total, and the serial numbers are 0,1,…,15; in this embodiment, as Figure 10 As shown, a NoC mapping method oriented to the dynamic and static combination of power consumption temperature is carried out as follows:

[0060] Step 1. Establish a mapping library through the discrete firefly algorithm for power consumption temperature:...

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Abstract

The invention discloses a power consumption and temperature oriented dynamic and static combined NoC (Network-on-Chip) mapping method. The method comprises the steps of 1, establishing a mapping library through a power consumption and temperature oriented discrete firefly algorithm; 2, storing the mapping library in a host; 3, sending an initial mapping scheme to an NoC by the host; 4, configuring a mapping scheme by the NoC; 5, monitoring communication traffic of each communication node in real time by the NoC and recording the communication traffic; 6, sending the communication traffic of the each node to the host periodically by the NoC; 7, calculating the temperature of each communication node by the host; 8, matching a temperature mode by the host according to the location of the node with the maximum temperature, and calling a corresponding mapping scheme in the mapping library; 9, sending a new mapping scheme to the NoC by the host; and 10, configuring the NoC by the NoC according to the new mapping scheme, and returning to the step 5. According to the method, a mapping hotspot is prevented from being generated, the network load is balanced, by adoption of the dynamic and static combined method, the online resource occupation is reduced, and the mapping optimization efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a NoC mapping method for dynamic and static combination of power consumption temperature. Background technique [0002] Although the change of network-on-chip (NoC) replacing the traditional bus structure overcomes various problems caused by the traditional structure to a certain extent, with the increase of IP (Intellectual Property) cores and the increase of communication traffic, the The power consumption of the interconnection network has become the focus of NoC design. With the reduction of the chip size and the improvement of the overall performance, the power consumption per unit area also increases. This makes the task mapped to the resource node for processing. The rapid rise even leads to the generation of local hot spots (Hot Spot); the high temperature affects the performance of the chip and may even damage the device, which greatly weakens t...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/08H04L12/26
CPCH04L43/08H04L67/63
Inventor 杜高明胡巧欧阳昊王晓蕾张多利宋宇鲲
Owner 黄山市开发投资集团有限公司