Fast test scheduling method

Abstract

The invention belongs to the technical field of test scheduling, and particularly relates to a fast test scheduling method which is short in test time and low in test cost. The method includes steps: 1) recording m test resources as jR(j=1, 2,...m), and recording n circuit modules which are tested objects as iC(i=1, 2,...n) wherein tests of modules are independent; 2) supposing that m1 tests n2, recording as T[1][2], and setting four features including test time t[1][2], test power consumption P[1][2], test speed ratio S[1][2] and test precedence relationship Pre[1][2]; if R2 cannot test C3, recording all of time, power consumption, speed ratio and precedence relationship of T[2][3] as -1; 3) allowing the m test resources to parallelly test the n tested objects.

Description

technical field [0001] The invention belongs to the technical field of test scheduling, in particular to a fast test scheduling method. Background technique [0002] SoC test problems include core test ring optimization, TAM optimization and test scheduling issues. The test scheduling algorithm refers to the cooperative optimization of the test package and the TAM to find the optimal test package design, TAM bandwidth allocation and IP test start time under the premise of fixed TAM bandwidth, so as to shorten the test time. The researchers used a variety of heuristic algorithms, including genetic algorithms, simulated annealing algorithms, and more. The study gives a detailed test scheduling scheme, which allows a trade-off between test power consumption and test time, and can avoid the problem of excessive power consumption in local areas on layout and routing. Many constraints are considered in this paper, including: the total power consumption of each core, physical / str...

AI Technical Summary

Problems solved by technology

Many constraints are considered in this paper, including: total power consumption of each core, physical / structural power consumption distribution, timing requirements and ATE bus width restrictions, etc., but the sharing of common resources is not considered

Using the shortest path algorithm, a system chip test scheduling algorithm based on embedded core design is given. Although the unified scheduling problem of general test resources is considered, the power consumption constraint and multi-time domain problem are not considered.

A multi-frequency test ring structure is designed to realize the testability of At-Speed, and a multi-clock SOC test scheduling method under the optimized TAM and test packet structure is proposed. Although these two articles consider the problem of multi-time domain clocks, they are limited to SCAN test, and does not consider issues such as shared resources and power consumption