Non-volatile memory cell with self aligned floating and erase gates, and method of making same

Abstract

A memory device and a method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. Any portion of the trench between the pair of floating gates is free of electrically conductive elements except for a lower portion of the erase gate.

Description

technical field [0001] The invention relates to a self-alignment method for forming a semiconductor memory array of floating gate memory cells. The invention also relates to a semiconductor memory array of floating gate memory cells of the aforementioned type. Background technique [0002] Nonvolatile semiconductor memory cells that use floating gates to store charge thereon and memory arrays of such nonvolatile memory cells formed in semiconductor substrates are well known in the art. Typically, such floating gate memory cells have been of the split gate or stacked gate type. [0003] One of the issues facing the manufacturability of semiconductor floating gate memory cell arrays is the alignment of various components such as source, drain, control gate and floating gate. As integrated design rules for semiconductor processing decrease, thereby reducing minimum lithographic features, the need for precise alignment becomes more critical. Alignment of various components al...

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Problems solved by technology

However, just forming the polysilicon block 50 requires a separate polysilicon formation step, which significantly increases the cost of production

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