Self-aligned interconnection structure and method

Abstract

The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer. An embodiment of the invention relates to the self-aligned interconnection structure and method.

Description

technical field [0001] Embodiments of the present invention relate to self-aligned interconnect structures and methods. Background technique [0002] In semiconductor processing, integrated circuit patterns may be defined on a substrate using photolithographic processes. The dual damascene process is used to form multilayer copper interconnects including vertical interconnect vias / contacts and horizontal interconnect metal lines. During the dual damascene process, a plug fill material is used to fill in the vias (or contacts), and then the material is polished back. However, the vias (or contacts) are defined by a different photolithographic process and can cause misalignment between the underlying metal lines and the vias. In particular, as semiconductor technology advances to advanced technology nodes with smaller feature sizes such as 20nm, 16nm, or less, misalignment is less tolerant and can lead to shorts, openings, or other problems. [0003] Therefore, the present ...

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Problems solved by technology

However, vias (or contacts) are defined by a different photolithographic process and can cause misalignment between underlying metal lines and vias

In particular, as semiconductor technology moves forward to advanced technology nodes with smaller feature sizes such as 20nm, 16nm or less, misalignment is less tolerant and can lead to shorts, openings or other problems

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