A High Speed ​​Low Offset Dynamic Comparator

Abstract

The invention provides a high-speed low-offset dynamic comparator comprising a dynamic differential comparison circuit, a comparator calibration circuit, a clock control circuit, a first switch, a second switch, a third switch, a fourth switch and a fifth switch, wherein the clock control circuit has a clock input end, a first clock output end and a second clock output end; the dynamic differential comparison circuit has a clock input end, a same-phase input end, an inverted-phase input end, a same-phase compensation control input end, an inverted-phase compensation control input end, a same-phase output end and an inverted-phase output end; and the comparator calibration circuit has a clock input end, a reset enable input end, a same-phase compensation output end, an inverted-phase compensation output end, a same-phase input end and an inverted-phase input end. The high-speed low-offset dynamic comparator provided by the invention can reduce the influence of a comparator offset voltage and is very suitable for the offset calibration of high-speed receivers.

Description

technical field [0001] The invention relates to a dynamic comparator, in particular to a high-speed low-offset dynamic comparator suitable for high-speed receivers. Background technique [0002] With the further development of information technology, the amount of data transmission has increased significantly, and the transmission speed has continued to increase. The design of high-speed receivers has become increasingly important. As a key module of high-speed receivers, comparators have a great impact on the performance of the entire receiver, such as speed, accuracy, and power consumption. Generally, high-speed comparators use a dynamic latch comparator structure to meet the speed requirements, but usually this type of dynamic comparator has a large offset voltage, which seriously restricts the accuracy of the dynamic comparator and limits the dynamic comparator in applications in high speed receivers. [0003] The offset calibration suitable for high-speed receivers ha...

AI Technical Summary

Problems solved by technology

Generally, high-speed comparators use a dynamic latch comparator structure to meet the speed requirements, but usually this type of dynamic comparator has a large offset voltage, which seriously restricts the accuracy of the dynamic comparator and limits the dynamic comparator in Applications in High Speed ​​Receivers

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