A Low Offset High Speed ​​Dynamic Comparator

Abstract

The invention discloses a low-offset and high-speed dynamic comparator. The low-offset and high-speed dynamic comparator comprises a primary pre-amplifier circuit for receiving an in-phase input signal, a reverse-phase input signal, a common-mode signal, an in-phase compensation control signal, a reverse-phase compensation control signal and a first clock control signal, and outputting a first in-phase output signal, a first reverse-phase output signal, and the first, second and third clock signals; a clock control circuit for receiving an external clock signal, outputting the first clock control signal and the second clock control signal; an offset calibration circuit for receiving the second in-phase output signal, the second reverse-phase output signal and the second clock control signal, and outputting the in-phase compensation control signal and the reverse-phase control signal; a fast latching circuit for receiving the first in-phase output signal, the first reverse-phase outputsignal and the first, second and third clock signals, and outputting the second in-phase output signal and the second reverse-phase output signal. The low-offset and high-speed dynamic comparator disclosed by the invention greatly improves the comparison speed of the comparator, and reduces the influence of the comparator offset voltage.

Description

technical field [0001] The invention relates to a dynamic comparator, in particular to a low-offset high-speed dynamic comparator suitable for high-speed analog-to-digital converters. Background technique [0002] With the further development of modern communication technology, the amount of data transmission has increased significantly, and the transmission speed has been continuously improved, which puts forward higher requirements for the design of high-speed analog-to-digital converters. As a key module of high-speed analog-to-digital converters, comparators have a great impact on the entire analog-to-digital converter with performance indicators such as speed, precision, and power consumption. For the traditional high-speed comparator based on the dynamic latch comparison structure, due to the large delay from the reset state to the positive feedback state during the latch process, the response speed of the comparator is severely limited, thus limiting the high-speed co...

AI Technical Summary

Problems solved by technology

For the traditional high-speed comparator based on the dynamic latch comparison structure, due to the large delay from the reset state to the positive feedback state during the latch process, the response speed of the comparator is severely limited, thus limiting the high-speed comparator performance of the dynamic comparator. Applications in Analog-to-Digital Converters

[0003] A high-speed comparator suitable for high-speed analog-to-digital converters has become an urgent problem to be solved. At the same time, a large offset voltage will affect the accuracy of the comparator. Therefore, a low-offset high-speed dynamic comparator is proposed to achieve higher performance. digital converter

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