The Implementation Method of Instruction Cache Consistency Based on Position Correspondence

Abstract

The invention relates to a method for realizing instruction Cache consistence based on position correspondence. Itag array and FB filling buffer in the same tissue structure are arranged on an instruction Cache management part and a second level Cache management part, wherein a virtual address is adopted by the instruction Cache management part and a physical address is adopted by the second level Cache management part. The method comprises the following steps: when instruction Cache missing of instruction access appears, firstly, applying for a V-FB filling buffer item and then applying for P-FB filling buffer item according to the V-FB filling buffer item; after the instruction Cache block data completely returns to the instruction Cache management part, starting to fill a V-Itag array by the V-FB filling buffer; after completely filling, filling the content onto a corresponding position of a P-Itage array by the P-FB filling buffer according to the position of filling the V-Itag array; and finally, enabling the P-FB filling buffer item and the V-FB filling buffer item to be invalid in turn. According to the invention, the consistence of the instruction Cache is realized.

Description

technical field [0001] The invention relates to the technical field of Cache consistency of microprocessors, in particular to a method for realizing instruction Cache consistency based on position correspondence. Background technique [0002] In modern microprocessors, Cache is already a standard configuration. Usually, there are instruction Cache (referred to as "I-Cache"), data Cache (referred to as "D-Cache"), secondary Cache (referred to as "L2-Cache"), and third-level Cache. Cache ("L3-Cache" for short), etc. To realize data intercommunication between caches, data consistency between caches must be maintained. Usually, D-Cache, L2-Cache or L3-Cache all have writable copies, and are stored in the form of physical addresses. The I-Cache is a read-only copy, which can be stored as a physical address or as a virtual address. [0003] To obtain writable permission for a copy, it is necessary to invalidate other caches that also have this copy. Usually, the criterion for ...

AI Technical Summary

Problems solved by technology

For CPUs that do not support instruction cache consistency, the way to invalidate the I-Cache is usually to refresh all the I-Cache and require software intervention, but the disadvantage of this is that the efficiency is low, and the refresh of the I-Cache will Some copies that do not need to be cleaned up are also cleaned up, causing unnecessary I-Cache loss and affecting performance

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