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A branch processing method and system

一种分支、处理器的技术，应用在电数字数据处理、程序控制设计、仪器等方向，能够解决性能损失等问题，达到消除效率损失的效果

Inactive Publication Date: 2017-07-28
SHANGHAI XINHAO MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, these prediction methods usually make predictions based on the previous operation results of the processor, so there will still be performance losses caused by prediction errors

Method used

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  • A branch processing method and system
  • A branch processing method and system
  • A branch processing method and system

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Embodiment Construction

[0030] Although the invention can be expanded in various forms of modification and replacement, some specific implementation illustrations are also listed in the description and explained in detail. It should be understood that the inventors' intention is not to limit the invention to the specific embodiments described, but on the contrary, the inventor's intention is to protect all improvements, equivalent transformations and modifications based on the spirit or scope defined by this claim. . The same element numbers may also be used throughout the drawings to represent the same or similar parts.

[0031] figure 2 An example of a pipelined control structure 1 consistent with the disclosed invention is shown. For ease of illustration, the pipeline operations include Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory Access (MEM) and Write Back (WB). Other pipeline structures may also be used. like figure 2 As shown, the decoder 11 fetches instructio...

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Abstract

The invention provides a branch processing method and system. A method for controlling pipeline operations of a processor is provided; the processor is connected with an instruction memory containing executable computer instructions; by investigating the executable computer instructions, instruction information at least containing branch information is extracted; a plurality of tracks are built according to the extracted instruction information; the addresses of branch target instructions are determined according to the multiple tracks; an unconditional jump mark is correspondingly added behind entries of the last instruction in the tracks, and a transfer target instruction thereof is an instruction closely following the last instruction in a program flow. The processor comprises two independent decoders; obtained two instructions are decoded by the two decoders separately; obtained instruction decoding results are sent to a selector and are selected by control signals from a branch judgment logic. An additional memory or read buffer and the instruction memory form a dual-port memory together.

Description

technical field [0001] The invention relates to the field of electronic computer and microprocessor architecture, in particular to a branch processing method and system. Background technique [0002] Control hazards, also known as branches, are a major cause of pipeline performance loss. When processing branch instructions, traditional processors cannot know in advance where to get the next instruction to be executed after the branch instruction, but need to wait until the branch instruction is completed to know, so that an empty cycle appears after the branch instruction in the pipeline. figure 1 is to show the traditional pipeline structure, where the pipeline segment corresponds to a branch instruction. [0003] Table 1 Pipeline segment of branch instruction (when branch transfer occurs) [0004] order i IF ID EX MEM WB i+1 IF stall stall stall Target IF ID EX MEM target +1 IF ID EX ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3844G06F9/3804G06F9/3806
Inventor 林正浩
Owner SHANGHAI XINHAO MICROELECTRONICS
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