Configuration code stream-based FPGA fault injection complex model

Abstract

The invention discloses a configuration code stream-based FPGA fault injection complex model. The model comprises a space traversal model, an environment reconstruction model, a fixed point accurate model, a resource guiding model and a multi-bit upset model, wherein the models obtain address information of corresponding target configuration bits on a configuration code stream layer of an FPGA in allusion to different research aims and different circuit designs, and carry out single-event upset fault injection on an FPGA circuit. The complex model disclosed by the invention is capable of estimating the sensitivity, to single-event upset effect, of the FPGA circuit from a plurality of angles such as entirety, locality, different research aims and different circuit types, overcoming the problem that the existing fault injection models are single in application range and application situation, and carrying out single-event upset fault injection on a part of the configuration bits, not all the configuration bits in a targeted manner so as to greatly improve the execution efficiency.

Description

technical field [0001] The invention relates to FPGA single event flipping fault injection, in particular to an FPGA fault injection compound model based on configuration code stream, which belongs to the field of FPGA reliability testing. Background technique [0002] FPGA circuits for space applications are susceptible to single-event upset effects in radiation environments, which can lead to data corruption in SRAM memory cells, thereby changing circuit functionality. The single event flip effect is produced by the impact of high-energy charged particles in the space on the SRAM unit of the FPGA. The mechanism is relatively complicated, and it is characterized in the configuration code stream, which is only manifested as the flip of the logic state of the configuration bit. Due to differences in the incident position of charged particles, particle energy, device technology, and circuit design, the single event inversion effect usually has two forms: one-bit inversion and ...

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Problems solved by technology

[0006] (3) The feature size of the device is reduced and the sensitivity is increased, resulting in the possibility of multi-bit flips that cannot be ignored. The existing fault injection model cannot realize multi-bit flips at one time;

[0007] (4) A single fault injection model is not suitable for the current research on the sensitivity of FPGA single event upset effect with multiple research purposes and multiple types of circuit design

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