Device based on extension IIC interfaces

Abstract

The invention discloses a device based on extension IIC interfaces. The device comprises an MCU and an extension board; N IIC signal channels are formed in the extension board, wherein N is an integer larger than or equal to 2; the first ends of the N IIC signal channels in the extension board are connected with the N IIC interfaces on the MCU respectively, and the second ends of the N IIC signal channels in the extension board are connected with N IIC buses respectively. The device circuit based on the extension IIC interfaces is simple in circuit, easy to implement and capable of improving the loading capacity of the IIC interfaces.

Description

technical field [0001] The invention relates to a device based on an extended IIC interface. Background technique [0002] IIC stands for Integrated Circuit Bus, which is a bidirectional, binary, synchronous serial bus. The bus is a multi-directional control bus. Multiple chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. The devices hanging on the IIC bus are divided into master and slave. The master is responsible for initializing the data of the IIC bus and generating a clock signal that allows transmission. The slave is a device that has a unique slave address and is addressed by the master. In view of the fact that IIC is easy to use and occupies less interface resources, it is becoming more and more popular in fields such as sensor data acquisition. [0003] In common application scenarios, multiple IIC slave devices are generally directly connected to the bus for communication. However, du...

AI Technical Summary

Problems solved by technology

These methods are mostly aimed at multiple slave device connection scenarios with the same non-modifiable slave address, but for limited access devices due to insufficient drive of IIC itself, or the bus transmission distance cannot be too far due to limited access capacitance of IIC itself, or Due to hardware limitations, it is impossible to access multiple bus level application scenarios, and no suitable solution is given; moreover, the above-mentioned patents often introduce other devices such as CPLD and FPGA, which increases the complexity of hardware routing and the difficulty of software programming

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