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logical address offset

A technology of logical address and memory unit, which is applied in the field of semiconductor memory devices and can solve the problems of not knowing the physical characteristics of memory arrays, etc.

Active Publication Date: 2019-06-18
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Some format utilities may not be aware of the physical characteristics of the memory array that makes up the SSD

Method used

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Embodiment Construction

[0015] The present invention includes methods, devices and systems for logical address offset. One method embodiment includes detecting a memory cell formatting operation. Then, in response to detecting the formatting operation, the method includes checking format information about the memory cell, calculating a logical address offset, and applying the offset to a host logical address.

[0016] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and which show by way of illustration how the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the invention, and it is to be understood that other embodiments may be utilized and that procedural, electrical, and / or structural changes. As used herein, the designators "N," "M," "R," and "S," especially with respect to reference numbers in the drawings, indicate...

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Abstract

The present invention includes methods, devices and systems for logical address offset. One method embodiment includes detecting a memory cell formatting operation. Then, in response to detecting the formatting operation, the method includes checking format information about the memory cell, calculating a logical address offset, and applying the offset to a host logical address.

Description

[0001] Information about divisional applications [0002] This case is a divisional application. The parent case of this divisional case is an invention patent application with an application date of January 15, 2010, an application number of 201080005160.5, and an invention title of “Logical Address Offset”. technical field [0003] The present invention relates generally to semiconductor memory devices, methods and systems, and more particularly to a logical address offset. Background technique [0004] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining st...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F12/02
CPCG06F3/0608G06F3/0638G06F3/0679G06F12/0246G06F2212/7202G06F12/02G06F12/06
Inventor 迈赫迪·阿斯纳阿沙里威廉·E·本森
Owner MICRON TECH INC