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a processor

A processor and decoder technology, applied in the computer field, can solve the problems of high probability of encryption algorithm being cracked and reduce the overall performance of the processor, save time, improve processing efficiency, and meet actual needs.

Active Publication Date: 2020-11-17
北京多思安全芯片科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the probability of this encryption algorithm being cracked is relatively high, and the implementation of the encryption algorithm greatly reduces the overall performance of the processor. security has been unable to meet the actual needs

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Embodiment Construction

[0038] In order to make the object, technical solution and advantages of the present invention clearer, the implementation manner of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0039] figure 1 is a structural diagram of a processor according to an embodiment of the present invention, see figure 1 , the processor 100 of this embodiment includes:

[0040] Instruction queue storage area 101, configuration information storage area 103, decoding control unit 102, explicit decoder 104 and implicit decoder 105;

[0041] The instruction queue storage area 101 is used to store the instruction queue to be decoded;

[0042] The configuration information storage area 103 is used to store decoding constraint information;

[0043] The decoding control unit 102 is used to read a plurality of instructions from the instruction queue storage area 101 as explicit instructions of the current decoding cycle at the beginning of...

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Abstract

The invention discloses a processor. The processor includes an instruction queue storage area, a configuration information storage area, a decoding control unit, an explicit decoder and an implicit decoder. The instruction queue storage area stores a to-be-decoded instruction queue. The configuration information storage area stores decoding constraint information. The decoding control unit reads a plurality of instructions from the instruction queue storage area at the beginning of each decoding cycle to use the same as explicit instructions of the current decoding cycle, and controls the explicit decoder to decode the explicit instructions according to the decoding constraint information in the configuration information storage area; and uses the instructions, which remains in the explicit instructions after the explicit instructions are decoded by the explicit decoder, as implicit instructions of the next decoding cycle at the end of the current decoding cycle, and controls the implicit decoder to decode the implicit instructions in the next decoding cycle. According to the embodiment of the invention, multi-instruction decoding is realized through logic circuit devices, a decoding control flow which can be continuously executed is formed, a decoding design is optimized, and the efficiency of instruction decoding and execution is improved.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a processor. Background technique [0002] Due to the rapid development of information technology, the importance of information security is increasing day by day. To keep information safe, processor security must be ensured. Security processor is a key technology in the field of information security. [0003] The current security processor mainly realizes the security processing of the processor by running encryption algorithm software. However, this kind of encryption algorithm has a high probability of being cracked, and the implementation of the encryption algorithm greatly reduces the overall performance of the processor. security has been unable to meet the actual needs. Contents of the invention [0004] In view of this, the present invention provides a processor to solve the above problems in whole or in part. [0005] A processor provided by the present inventio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30
CPCG06F9/30101G06F9/30145G06F9/30196
Inventor 刘大力曹春春
Owner 北京多思安全芯片科技有限公司
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