Dividing method and device of memory space of flash memory in field-programmable gate array
A storage space and gate array technology, applied in the direction of input/output to record carrier, etc., can solve the problems of increasing the cost of FPGA system, restricting the convenience and flexibility of FPGA data storage, and waste of space, so as to improve convenience and flexibility , Avoid space waste and reduce cost
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[0046] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
[0047] figure 1 For the connection schematic diagram of field programmable gate array FPGA and flashing memory FLASH according to an embodiment of the present invention, below in conjunction with figure 1 To describe in detail the connection relationship between the Field Programmable Gate Array FPGA and the flash memory FLASH according to an embodiment of the present invention, as figure 1 As shown, FPGA and parallel FLASH are interconnected, where:
[0048] The clock output port CLK of the FPGA is connected to the clock input port of the parallel FLASH;
[0049] The chip select output...
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