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Modulating processor core operations

A processor and core processor technology, applied in electrical digital data processing, architectures with multiple processing units, instruments, etc., can solve problems such as deduction of computing power, and achieve the effects of reducing negative effects, improving performance, and low latency

Active Publication Date: 2018-01-26
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, dedicating a processor to specific I / O operations can deprive a large amount of computing power from a multicore processor

Method used

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  • Modulating processor core operations
  • Modulating processor core operations

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Embodiment Construction

[0012] The systems and methods described below relate to dedicating individual processor cores within a multi-core CPU (eg, a processor) to achieve low latency and increase overall general-purpose processor core performance. In some implementations, a first set of processor cores of the multi-core processor is dedicated to performing low-latency operations. For example, low-latency operations may include input / output (I / O) operations, accessing data in memory (e.g., solid-state drives, flash memory devices, etc.) that communicate with other processor cores, such as for exchanging very fast messages ( For example, 1μS-100μS) non-volatile storage technology of supercomputing network structure and other low-latency operations. The second set of processor cores in a multi-core processor are processor cores that are not limited to performing only low-latency operations, for example, the second set of processor cores can perform a large number of different operations required by the...

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Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes amulti-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less thann, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Description

technical field [0001] This specification relates to techniques for modifying the performance of a processor. Background technique [0002] Modern computer processors typically include multiple independent processor cores. Current computing systems have been optimized for efficiently processing , forecast, etc.) events. [0003] Efficiently supporting events that take a few microseconds, especially when low-latency response times are required, remains a challenge. Such microsecond granular events are becoming more common with high-performance networking fabrics, new non-volatile storage technologies such as flash and phase-change memory, or data exchange utilizing computing accelerators such as graphics processing units (GPUs). Microsecond events are too short to afford the overhead of context switches and operating system interrupts, and too long to be easily addressed by hardware processor architectural features in today's microprocessors. [0004] Dedicating processor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/80G06F9/50
CPCG06F9/5061Y02D10/00G06F15/80
Inventor 鲁兹·安德烈·巴罗索
Owner GOOGLE LLC