A Simplified Method of Symbol Timing Synchronization in OFDM System Receiver

Abstract

The invention discloses a symbol timing synchronization simplification method for an OFDM system receiver, and the method is a symbol timing synchronization method based on a special training sequence, and comprises the following steps: carrying out the accumulation of the absolute values of signal values Rn+k of all bits of a received signal, and obtaining a first operation result; carrying out the sign optimization calculation of the values Tk of all sign bits of a local special sequence with the length of 1, carrying out the multiplying of the signal values Rn+k of all bits of the receivedsignal and the sign (Tk) values, carrying out the accumulation, obtaining the absolute value, and obtaining a second calculation result; dividing the second calculation result by the first calculationresult, and obtaining a sign timing signal after the peak detection of a dividing result Q'n. The method provided by the invention simplifies the sign timing synchronization algorithm based on the training sequence and a hardware implementation structure.

Description

technical field [0001] The invention relates to the communication field, in particular to a simplified method for symbol timing synchronization in an OFDM system receiver. Background technique [0002] Orthogonal Frequency Division Multiplexing (OFDM) is a high-speed transmission technology in a wireless environment. The core of the technology is to divide the channel into several orthogonal sub-channels, convert high-speed data signals into parallel low-speed sub-data streams, and modulate them for transmission on each sub-channel. Orthogonal signals can be separated by using correlation techniques at the receiving end, which can reduce the mutual interference between sub-channels. The signal bandwidth on each subchannel is smaller than the relevant bandwidth of the channel, so each subchannel can be regarded as flat fading, which can eliminate intersymbol interference, and since the bandwidth of each subchannel is only a small part of the original channel bandwidth, chann...

AI Technical Summary

Problems solved by technology

When a general digital multiplier is implemented, both the multiplier and the multiplicand are quantized into signed or unsigned numbers with a width of n bits. In this way, the wider the quantization bit width, the higher the complexity of the multiplication operation.

[0010] Although there are currently various simplified algorithms, they are basically aimed at the simplification of back-end peak detection and detection methods, and the real operations of front-end multiplication and accumulation are difficult to bypass.

The hardware implementation of this symbol timing synchronization algorithm is very complex

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