A kind of adc structure and its analog-to-digital conversion method based on multi-phase clock

Abstract

The invention discloses an ADC structure based on a multi-phase clock and an analog-to-digital conversion method thereof. The ADC structure includes a ramp wave generation module, a clock generation module, a comparator module, a counting module and a data processing module. The comparator module There are two input ports and one output port, one input port of the comparator module is connected to the analog signal, the other input port is connected to the ramp signal, the output port of the comparator module is connected to an input port of the counting module connected; the other input terminal of the counting module is connected with a multi-phase clock, the output terminal of the counting module is connected with the input terminal of the data processing module, and the output terminal of the data processing module outputs the converted digital signal . The multi-phase clock-based ADC structure and its analog-to-digital conversion method provided by the present invention can greatly increase the conversion rate of the ADC, and can save chip area and dynamic power consumption.

Description

technical field [0001] The invention relates to the field of CMOS integrated circuit design, in particular to an ADC structure based on a multiphase clock and an analog-to-digital conversion method thereof. Background technique [0002] With the development of CMOS integrated circuit technology, electronic products are more and more widely used in daily life and become an indispensable part of various fields. Among them, the electronic products corresponding to the image sensor, with the continuous increase of definition and pixels, high frame rate has become one of the important parameters of the image sensor, and the conversion rate of the ADC in the image sensor is called an important factor limiting the frame rate, ADC The faster the conversion rate, the highest maximum frame rate the image sensor can achieve. [0003] In order to obtain a faster ADC conversion rate, researchers usually make a fuss about a higher clock frequency or a more complex structure, but the high...

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Problems solved by technology

[0003] In order to obtain a faster ADC conversion rate, researchers usually make a fuss about a higher clock frequency or a more complex structure, but the higher the clock frequency, the greater the dynamic power consumption, and the complex ADC structure is often accompanied by more Large power consumption and chip area, which has caused great restrictions on the promotion and use of image sensors

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