Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Testing method and device of memory

A test method and memory technology, applied in static memory, instruments, etc., can solve the problems of single test process, cumbersome operation process, incomplete test, etc., and achieve the effect of improving accuracy and efficiency and ensuring comprehensiveness

Active Publication Date: 2018-06-05
GIGADEVICE SEMICON (BEIJING) INC
View PDF4 Cites 7 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the validity verification process, specific test commands, including specific read and write lengths, specific operation addresses, specific access areas, etc., will lead to a relatively simple test process and cannot achieve comprehensive testing
When a problem occurs in the test, it is necessary to reproduce the test command to test the repaired program. In the prior art, the test can only be performed through the operation instructions in the specific test sequence, resulting in incomplete testing and cumbersome operation process.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Testing method and device of memory
  • Testing method and device of memory
  • Testing method and device of memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] figure 1 It is a flow chart of a memory testing method provided by Embodiment 1 of the present invention. The method is applicable to the case of performing a function test on the memory, and the method can be executed by a memory testing device, and the device can be realized by software and / or hardware. The method specifically includes:

[0054] S110. Obtain at least one operation instruction according to a preset pseudo-random function, respectively number the operation instructions in sequence, and arrange the operation instructions in the order of the numbers to form a test sequence.

[0055]Specifically, a pseudo-random function is a type of function. A function describes the correspondence between each input value and a unique output value. The pseudo-random function is used to generate a pseudo-random number. The random function is a function that generates numbers, and it is an important random function in Excel worksheets and C language. The most important ...

Embodiment 2

[0064] figure 2 It is a flow chart of a memory testing method provided by Embodiment 2 of the present invention. This embodiment is optimized on the basis of the above embodiments, and optimizes "obtaining at least one operation instruction according to a preset pseudo-random function" , including the following steps:

[0065] S210. Adjust an input parameter of the pseudo-random function to obtain a random number corresponding to the input parameter one by one, wherein the value of the input parameter and the random number are at least one.

[0066] Specifically, there may be two input parameters of the pseudo-random function, denoted as A and B, and A and B may each have at least one value, and the generated pseudo-random number is Y. Among them, A is used to provide seeds, and B is used to generate random numbers. Different seeds will generate different random numbers. The same seed and different input parameters B will generate different random numbers. A and B can take ...

Embodiment 3

[0088] image 3 It is a flowchart of a fault detection method for a downhole control system provided by Embodiment 3 of the present invention. This embodiment is optimized on the basis of the above embodiments. For "if an error is detected in the memory, use the The test sequence "retest the repaired memory" has been optimized, which includes the following steps:

[0089] S310. Obtain at least one operation instruction according to a preset pseudo-random function, respectively number the operation instructions in sequence, and arrange the operation instructions in the sequence of numbers to form a test sequence.

[0090] S320. Execute the operation instructions in the test sequence according to the numbering order to test the memory.

[0091] S330. Obtain the operation instruction corresponding to the error point and the serial number of the operation instruction corresponding to the error point in the test sequence.

[0092] S340. If the length of the test sequence is great...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The embodiment of the invention discloses a testing method and device of a memory. The method includes: acquiring at least one operation instruction according to a preset pseudo-random function, respectively numbering the operation instruction in an orderly manner, and arranging the operation instruction according to a number order to form a testing sequence; executing the operation instruction inthe testing sequence according to the number order to test the memory; and utilizing the testing sequence to retest the repaired memory if occurrence of an error of the memory is detected. Random testing on memory programs and / or data is realized, comprehensiveness of testing is guaranteed, and accuracy and efficiency of testing are improved.

Description

technical field [0001] The embodiments of the present invention relate to the field of digital testing, and in particular to a memory testing method and device. Background technique [0002] The main function of the memory is to store programs and various data, and to complete the program or data access at high speed and automatically during the operation of the computer. Before the memory can be used, it needs to be functionally tested. In prior art memory testing, developers usually determine the type and test order of each operation instruction in the test sequence, and test programs and data of a specific length and a specific access area in the memory. [0003] During the testing process, the data of the program to be tested is huge, and the problems that arise are also random. In the validity verification process, specific test commands, including specific read and write lengths, specific operation addresses, specific access areas, etc., will lead to a relatively sim...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
CPCG11C29/56
Inventor 王立峰
Owner GIGADEVICE SEMICON (BEIJING) INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com