Verification platform of system-on-chip and verification method thereof

A system-level chip and verification platform technology, which is applied to the verification platform of the system-level chip and its verification field, can solve the problems of affecting the test coverage rate, affecting the simulation progress, and the difficulty of direct testing, etc.

Pending Publication Date: 2021-12-31
MONTAGE TECH CHENGDU CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In this way, in order to achieve test coverage, it takes a lot of time to build a large number of direct tests, which affects the simulation progress
At the same time, direct testing of some scenarios is extremely difficult or even impossible to build manually, which affects the improvement of test coverage
Moreover, since the software program cannot dynamically control the verification platform, each time a simulation of a verification platform configuration is started, it needs to be recompiled, which affects the efficiency of the simulation.

Method used

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  • Verification platform of system-on-chip and verification method thereof
  • Verification platform of system-on-chip and verification method thereof
  • Verification platform of system-on-chip and verification method thereof

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Embodiment Construction

[0022] Various aspects and examples of the application will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. However, it will be understood by those skilled in the art that this application may be practiced without many of these details.

[0023] Also, some well-known structures or functions may not be shown or described in detail for the sake of brevity and to avoid unnecessarily obscuring the related description.

[0024] Explanation of some concepts:

[0025] IP core module: IP (Intellectual Property) core module is a pre-designed or even verified component with certain functions, which can be integrated and selected by chip designers. Generally, there are multiple IP core modules integrated in SoC.

[0026] Coverage: Coverage is a measure of test integrity and a measure of test effectiveness. Coverage is equal to the number of items executed at least once / total number of items....

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Abstract

The invention discloses a verification platform and a verification method for a system-on-chip. The method comprises the following steps: generating constrained random parameters and random control by a general verification methodology test instance, and storing the random parameters and the random control in a storage area of a bus function model; allowing a software test instance to read the random parameters from the storage area through a central processing unit and randomly control the test of the configuration system-on-chip; storing the execution state information of the software test instance in the storage area; and allowing the general verification methodology test instance to read the execution state information, generate random parameters and constraint conditions of random control according to the execution state information so as to exclude a tested scene, and convert the execution state information into coverage rate data for coverage rate analysis.

Description

technical field [0001] The invention generally relates to the technical field of simulation verification, and in particular to a system-level chip verification platform and a verification method thereof. Background technique [0002] SoC (System on Chip, system-on-chip) technology refers to the integration of a central processing unit (CPU), input and output (I / O) peripherals, memory, and other functional peripherals into one chip. SoC technology can effectively reduce product area, improve product performance, reduce product power consumption, and improve product reliability, so it has been widely used. However, due to the high cost of the chip, in order to ensure the function and performance of the SoC chip, a large number of sufficient verifications are required before the chip is taped out. [0003] A kind of mode of SoC chip verification in the prior art is: execute test mode by CPU, require to run software program on CPU, configure the object under test by software pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33G06F115/08
CPCG06F30/33G06F2115/08G06F2115/02G06F30/398G06F11/00G06F30/20G06F30/3308G01R31/28G06F30/367
Inventor 毛惠敏李顺林
Owner MONTAGE TECH CHENGDU CO LTD
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