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Versatile Execution Channel for Image Processors

A technology of image processing and execution unit, applied in the field of computing science, which can solve problems such as lack of solutions

Active Publication Date: 2021-11-16
GOOGLE LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] A technology platform that offers highly versatile application software development opportunities coupled with increased power efficiency per unit of data remains a desired but missing solution

Method used

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  • Versatile Execution Channel for Image Processors
  • Versatile Execution Channel for Image Processors
  • Versatile Execution Channel for Image Processors

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0016] figure 1 An embodiment of a stencil processor architecture 100 is shown. A template processor, as will be more clearly described in the following discussion, is a processor optimized or otherwise designed to process templates of image data. One or more template processors may be integrated into the image processor, which perform template-based tasks on the image processed by the processor. as in figure 1 As seen in , the template processor includes a data computation unit 101 , a scalar processor 102 , and associated memory 103 and I / O unit 104 . The data computing unit 101 includes an array of execution channels 105, a two-dimensional shift array structure 106, and individual random access memories 107 associated with specific rows or columns of the array.

[0017] The I / O unit 104 is responsible for loading the received input "form" of image data into the data calculation unit 101 and storing the output data form from the data calculation unit external to the templ...

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Abstract

An apparatus is described that includes an execution unit having a multiply-add computation unit, a first ALU logic unit, and a second ALU logic unit. The ALU unit is used to execute a first instruction, a second instruction, a third instruction, and a fourth instruction. The first instruction is a multiply-add instruction. A second instruction is used to perform a parallel ALU operation to generate a different corresponding output result of the second instruction if the first and second ALU logic units operate simultaneously. The third instruction is for performing sequential ALU operations to determine an output result of the third instruction if one of the ALU logic units operates on an output of another of the ALU logic units. The fourth instruction is for performing an iterative division operation, wherein the first ALU logic unit and the second ALU logic unit perform operations to determine first and second division result bit values.

Description

technical field [0001] The technical field of the invention relates generally to computing science, and more specifically to multifunctional execution channels for image processors. Background technique [0002] Image processing often involves manipulation of pixel values ​​organized into arrays. Here, a spatially organized two-dimensional array captures the two-dimensional nature of the image (additional dimensions may include time (e.g., a sequence of two-dimensional images) and data type (e.g., color). In a typical scenario, an array of pixel values Provided by a camera that has generated a still image or a frame sequence of images that capture motion. Traditional image processors typically fall on either side of the two extremes. [0003] A first extreme performs image processing tasks as software programs executing on a general-purpose processor or similar general-purpose processor (eg, a general-purpose processor with vector instruction enhancement). While the first ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/57
CPCG06F7/57G06F9/3001G06F9/30014G06F15/80G06F9/3877G06F9/3893G06F9/3887G06F9/3885
Inventor 阿蒂姆·瓦西里耶夫杰森·鲁珀特·莱德格雷夫阿尔伯特·迈克斯纳奥弗尔·莎查姆
Owner GOOGLE LLC