Unlock instant, AI-driven research and patent intelligence for your innovation.

Improved cache pseudo-least recently used data replacement method

A cache, the least recent technology, applied in the direction of memory address/allocation/relocation, etc., can solve problems such as high overhead

Inactive Publication Date: 2018-06-19
UNIV OF ELECTRONIC SCI & TECH OF CHINA
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when N>2, it is necessary to maintain the data access sequence stack, which becomes extremely expensive for digital logic hardware, that is, to complete operations and store information

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Improved cache pseudo-least recently used data replacement method
  • Improved cache pseudo-least recently used data replacement method
  • Improved cache pseudo-least recently used data replacement method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0014] In a tree control structure, each leaf node (identifying a certain way of the cache) contains 1 to 2 flag bits, that is, each way has one or two flag bits. If there is only one bit, the value of the flag bit is 0 or 1, and if there are two bits, the values ​​of the two flag bits are 0 and 1, respectively. This is because the flag bits of different error-introducing nodes are not necessarily the same.

[0015] The flag bits are named as follows: take the analyzed error-introduced node as the root node, all paths in its left subtree have flag bits 0 for it, and all paths in its right subtree have In other words, the flag bits are all 1. In this way, except that way 1 and way N only contain one flag bit of 0 and 1 respectively, the other ways all contain two flag bits of 0 and 1, which are respectively aimed at different error introduction nodes. The flag bits of the same path for the same error-introducing node may also be the same as the flag bits of this path for othe...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to an improvement of a pseudo-least recently used replacement method of a multi-channel group connection cache framework. A small number of extra registers and a small number ofmarker bits are used for improving the pseudo-least recently used replacement method of a cache, so that the pseudo-least recently used replacement method is closer to a real pseudo-least recently used replacement method. By increasing the number of channels, requirements for record values of auxiliary shift registers of nodes, close to a root node, of a pseudo-least recently used control tree canbe properly reduced, so that conjecture selection is conducted when replacement data is selected.

Description

technical field [0001] The present invention relates to a processor cache replacement unit and a replacement method on a miss. And it particularly relates to an N-way set-associative (N≥4) architecture and a cache data replacement component and replacement method using a pseudo-least recently used (LRU) replacement strategy. Background technique [0002] Modern processor architecture usually uses cache (cache) as the backup of memory data. When the processor reads data, it usually reads in the cache with faster reading speed first, so as to shorten the cycle of data acquisition, thereby Speed ​​up your processor. As a backup place for memory data, the mapping between cache and memory can generally be divided into fully associative mapping, direct associative mapping and set associative mapping. Compared with fully associative mapping and direct associative mapping, group associative mapping can provide better performance in most applications, especially in multiprocessor a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F12/12
CPCG06F12/12
Inventor 梁成豪黄乐天
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA