A Segmented Programmable Clock Network Architecture Based on Clock Regions

Abstract

The invention discloses a segmented programmable clock network structure based on clock regions. The clock network structure includes a wiring clock and a distribution clock. The wiring clock ensures the path delay from the clock source to the root clock node in different clock regions through the programmable feature. The timing is the same, thus providing a high-performance clock signal with almost zero skew. There are n routing clocks and n distribution clocks passing through each clock region in the vertical direction and the horizontal direction respectively, and the value of n can be adjusted. Routing a clock connects the clock input port, sends the clock signal to the clock root node in the clock region, and then sends the clock signal to all parts of the clock region by distributing the clock. The clock region adopts a fishbone clock network structure, and each leaf node clock is driven by a distributed clock enable. The invention is suitable for large-scale high-performance FPGA, can provide low-offset high-performance clock signal, and satisfies the demand of large-scale FPGA chip for high-performance clock.

Description

technical field [0001] The invention relates to a clock network structure suitable for a large-scale FPGA structure, in particular to a segmented programmable clock network structure based on clock regions, and belongs to the technical field of programmable logic devices. Background technique [0002] FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) devices have the advantages of short development cycle, low cost, low risk, high integration, high flexibility, and easy maintenance and upgrade of electronic systems, so they are widely used in terminal products. Favored by users, it has become the mainstream of integrated circuit chips, and is widely used in various fields, such as communication, control, video, information processing, electronics, Internet, automobiles and aerospace, and is also widely used in the prototype of integrated circuits Validation, reducing product development time. [0003] With the continuous improvement of the technology level,...

AI Technical Summary

Problems solved by technology

However, due to the characteristic of clock skew accumulation in this architecture, the operating frequency of the clock is often limited when it is applied in a large-capacity, high-performance FPGA.

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