Performance benefit evaluation method of lru Cache prefetch mechanism based on artificial neural network

Abstract

The invention discloses a performance benefit evaluation method of an LRU Cache prefetching mechanism based on an artificial neural network. The neural network training parameters are selected to fit the distribution of access stack distances before the introduction of the prefetching mechanism and the number of missing Cache accesses after the introduction of the prefetching mechanism. , construct a neural network model; calculate the target stack distance distribution of the target program; import the calculated target stack distance distribution into the constructed neural network model, and predict the number of cache access misses of different target programs under the current prefetching mechanism; use the stack distance distribution Calculate the number of cache access misses before the introduction of the prefetch mechanism, compare the predicted number of cache access misses under the current prefetch mechanism with the number of cache access misses before the introduction of the prefetch mechanism, and evaluate the performance benefits of the prefetch mechanism. It can greatly improve the prediction speed of the performance benefit of the Cache prefetch mechanism.

Description

technical field [0001] The invention belongs to the technical field of computer architecture and modeling, and in particular relates to a method for evaluating the performance benefit of an LRU Cache prefetching mechanism based on an artificial neural network. Background technique [0002] Pre-silicon architecture evaluation and design space exploration based on hardware behavior modeling can provide guidance for chip design and reduce the iterative cycle of chip design. Under the modern processor architecture, the introduction of on-chip cache (Cache) can speed up memory access and improve CPU operating efficiency. However, the lack of Cache access will cause bubbles in the processor pipeline and even cause pipeline blockage, thereby reducing the computing performance of the processor. In order to improve the Cache access hit rate, the Cache design will introduce instruction or data prefetching to move the content that may be accessed in the future to the Cache in advance....

AI Technical Summary

Problems solved by technology

The disadvantage is that the obtained stack distance distribution can only reflect the characteristics of the memory access instruction flow at the software logic level, so the stack distance distribution cannot be directly applied to the Cache behavior modeling using the prefetch mechanism, but it can be used for Cache access before the prefetch mechanism is introduced. Missing count prediction

To put it simply, the prefetching mechanism will change the historical access records of the Cache, thereby affecting the calculation of the stack distance, so that the calculated number of Cache access misses deviates from the real scene

Although clock-accurate simulation can accurately predict the performance benefits of prefetching mechanisms, the simulation cycle is too long, which is not conducive to quickly evaluating Cache memory access behavior and design space exploration

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