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Disorder and calibration method suitable for SAR ADC with non-loop structure

A calibration method, a non-loop technology, applied in the direction of analog/digital conversion calibration/test, electrical components, code conversion, etc., can solve problems such as comparator offset, comparator mismatch, and multiple comparator calibration effects, and achieve SFDR Improve, reduce the stabilization time, save the effect of hardware consumption

Active Publication Date: 2018-09-14
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art, provide a disorder and calibration method suitable for non-loop structure SAR ADC, and solve the problem that the introduction of multiple comparators will cause comparator imbalance and Mismatch between, making the calibration of multiple comparators affected

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  • Disorder and calibration method suitable for SAR ADC with non-loop structure
  • Disorder and calibration method suitable for SAR ADC with non-loop structure
  • Disorder and calibration method suitable for SAR ADC with non-loop structure

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Embodiment Construction

[0031] Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0032] Such as figure 1 Shown is the overall structural frame diagram of the calibration method of the present invention applied to 8bit SAR ADC, including 9 comparators COMP1~COMP9, a reference comparator REFCOMP, and out-of-sequence and calibration control logic.

[0033] Nine of the comparators and the reference comparator are used as figure 2 The structure shown specifically includes MP1a, MP1b, MP2a, MP2b, MN1, MN2a, MN2b, MN3a, MN3b, MN4a, and MN4b, wherein MP1a, MP1b, MP2a, and MP2b are PMOS tubes, and MN1, MN2a, MN2b, MN3a, MN3b , MN4a and MN4b are NMOS tubes.

[0034] Such as figure 2 In the shown circuit structure, the source of MP1a is connected to the source of MP1b, the source of MP2a and the source of MP2b, and its connection point is connected to the power supply VDD; the gate of MP1a is connected to the drain of MP2b, the drain of MN4a The ...

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Abstract

The invention discloses a disorder and calibration method suitable for an SAR ADC with a non-loop structure. The method comprises the following steps of carrying out foreground calibration on a reference comparator in an ADC, namely comparing a positive input end and a negative input end of the reference comparator, and increasing a voltage value according to a comparison result in order to compensate an offset; carrying out disorder operation on the comparator in each conversion cycle, and selecting one for comparing an MSB bit of the second conversion by adopting a pseudo random number sequence; and calibrating the comparator after the disorder operation, namely judging whether the current comparison cycle is an LSB bit comparison, if yes, comparing the output result of the reference comparator and the output result of the LSB bit comparator, and increasing calibration voltage input by the LSB bit comparator according to the comparison result. According to the method, the calibrationis carried out by comparing the output result of the LSB bit comparator after disorder with the output result of the fixed reference comparator, the additional time is not increased, and the convergence speed of a calibration algorithm is accelerated.

Description

technical field [0001] The invention relates to a random sequence and calibration method suitable for non-loop structure SAR ADC, belonging to the technical field of SAR ADC. Background technique [0002] High-speed and low-power analog-to-digital converters are widely used in the communication field. Traditional SAR ADCs are limited by their working principles, making it difficult to achieve high-speed performance. In recent years, with the continuous development of advanced technology, SAR ADC has benefited from its high degree of digitality, and its speed can be relatively high. Many studies have devoted themselves to greatly increasing the speed of SAR ADC through structural improvements. Among them, the non-loop structure uses a separate comparator to work in each comparison cycle, which greatly reduces the logic delay of the traditional loop structure and improves the conversion speed. However, the introduction of multiple comparators will cause the offset of the comp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1009
Inventor 吴建辉包天罡孙杰李红王鹏王甫锋
Owner SOUTHEAST UNIV