A data read and write access control method and device
A technology of access control and data reading and writing, applied in the electronic field, can solve the problems of long interval between reading and writing switching, performance loss of reading and writing switching, and increased production cost, so as to improve the utilization rate of data reading and writing and reduce the cost of PCB production , The effect of saving DRAM capacity
Active Publication Date: 2022-02-18
HUAWEI TECH CO LTD
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Problems solved by technology
[0003] In practice, it is found that under the multi-channel structure, if multiple commands with the same identifier are sent to different channels, or commands are split and sent to different channels, the service latency will be increased, thereby affecting system performance; while in multi-rank Under the structure, reading and writing switching between ranks will cause performance loss, and the time interval between reading and writing switching is relatively large, which will reduce the utilization rate of system data reading and writing
And under the multi-channel structure or multi-rank structure, due to the increase of the DMC or the increase of the rank of the DMC, the chip area increases, resulting in an increase in chip production costs and an increase in the production cost of the printed circuit board (Printed Circuit Board, PCB).
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[0033] Embodiments of the present invention will be described below with reference to the accompanying drawings.
[0034] The embodiment of the invention discloses a data read-write access control method and device. In the asymmetric capacity DRAM splicing scheme, the data read and write utilization rate of the DDR DRAM system can be improved, the business latency period can be reduced, and the chip production cost and PCB production cost can be reduced at the same time.
[0035] In order to better understand the data read / write access control method and device disclosed in the embodiments of the present invention, the architecture of the DDR DRAM system applicable to the embodiments of the present invention will be described below. see figure 1 , figure 1 It is a schematic structural diagram of a DDR DRAM system disclosed by an embodiment of the present invention. exist figure 1 In the shown architecture, the DDR DRAM system includes a central processing unit (Central Pro...
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The embodiment of the invention discloses a data read-write access control method and device. Applied to the DDR DRAM system, a data read and write access control device is added in the system, the device is connected to the processor and the DMC, the first DRAM and the second DRAM are connected to the CS signal pin in the DMC, and the first DRAM is controlled by the first DRAM. The capacity area is composed of a second capacity area, the capacity of the second capacity area is equal to the capacity of the second DRAM, and the first address area includes the second capacity area and the capacity area of the second DRAM. The method includes: when the device receives the target command, it judges the range of the access address of the target command, and if it belongs to the first address area, based on the target command and the access address, it controls the DMC to control the read and write access to the data in a symmetrical storage capacity manner. In this way, the data read and write utilization rate of the DDR DRAM system can be improved in terms of performance, and the service latency can be reduced.
Description
technical field [0001] The invention relates to the field of electronic technology, in particular to a data read-write access control method and device. Background technique [0002] Among common chip products, a Double Data Rate (Double Date Ration, DDR) Dynamic Random Access Memory (DRAM) system can be spliced using DRAM devices with symmetric capacity or DRAM devices with asymmetric capacity. Among them, in the splicing scheme of asymmetric capacity DRAM devices, a multi-channel structure can usually be adopted, and each dynamic memory controller (Dynamic Memory Controller, DMC) is a channel, and the data, commands, clock reset and other signals of each channel are completely Independent; multi-group structure (that is, multi-rank structure) can also be used. The chip selection (Chip Selection, CS), clock enable (Clock Enable, CKE), and on-chip terminator (On-DieTermination, ODT) signals of each group are independent. [0003] In practice, it is found that under the m...
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IPC IPC(8): G06F13/16
CPCG06F13/1668
Inventor吴汉利
OwnerHUAWEI TECH CO LTD