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Wafer test device and method

A chip testing, chip technology, applied in the direction of measuring devices, electronic circuit testing, measuring electricity, etc., can solve the problems of low tester frequency and inability to test high-frequency chips, and achieve the effect of saving testing costs

Pending Publication Date: 2018-12-07
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present disclosure is to provide a chip testing device and a wafer testing method, and then at least to a certain extent overcome the problem that the wafer cannot be tested at high frequency due to the low frequency of the tester in the related art

Method used

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  • Wafer test device and method
  • Wafer test device and method
  • Wafer test device and method

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Embodiment Construction

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the description in the accompanying drawings directions for the example described above. It will be appreciated that if the illustrated device is turned over so...

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Abstract

The invention relates to a wafer test device and method. The test device comprises an interface card, wherein the interface card comprises a signal synthesis device, multiple first interfaces and a second interface, the signal synthesis device is used for synthesizing first signals emitted by multiple detectors into a second signal and transmitting the second signal to a wafer socket, the multiplefirst interfaces are arranged at an input end of the signal synthesis device and is used for connecting the multiple detectors, and the second interface is arranged at an output end of the signal synthesis device and is used for connecting the wafer socket. The test device is advantaged in that the first signals having low frequency emitted by the multiple detectors are synthesized by the signalsynthesis device into the second signal, and high-frequency test of a wafer is achieved through utilizing the multiple low frequency detectors.

Description

technical field [0001] The present disclosure relates to the technical field of chip testing, in particular, to a chip testing device and a wafer testing method. Background technique [0002] With the development and progress of technology, wafers are widely used in various integrated circuits, and it is usually necessary to test the wafers before use. In the internal memory, the requirements for the operation speed of the internal memory chips are getting higher and higher, correspondingly the requirements for the operation speed of the chips are also higher and higher, and the frequency requirements for the testing device are also higher and higher during the test. [0003] At present, the frequency of testers used in production cannot meet the high-frequency testing requirements of wafers. [0004] It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and ther...

Claims

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Application Information

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IPC IPC(8): G01R31/28
CPCG01R31/2856
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC
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