A fpga/ip core logic code security rule detection method

A technology of rules and codes, which is applied in the field of FPGA/IP core logic code security rule detection, can solve problems such as lack of security rule sets, achieve the effect of reducing invalid warning rules and improving quality

Active Publication Date: 2021-07-02
BEIJING INST OF COMP TECH & APPL
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  • Description
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Problems solved by technology

Missing some security rule sets for programmable devices

Method used

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  • A fpga/ip core logic code security rule detection method
  • A fpga/ip core logic code security rule detection method
  • A fpga/ip core logic code security rule detection method

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Embodiment Construction

[0051] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0052] Aiming at the problem that the current static rule detection method lacks a subset of programmable device security rules, the present invention proposes a relatively complete set of comprehensive rule detection methods, which can be applied to the logic code security rule detection of FPGA / IP cores, and effectively detect FPGA or The standardization of the RTL code of the IP core. Such as figure 1 Shown, FPGA / IP core logic code security rule detection method of the present invention comprises the following steps:

[0053] Step 1: Input the Verilog HDL code of the FPGA to be verified and use commercial tools (such as LEDA, Alint, Autocheck) to perform routine rule detection, and obtain the routine rule detection...

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Abstract

The invention relates to a method for detecting safety rules of FPGA / IP core logic codes, and relates to the technical field of FPGA / IP core verification. According to the combination of the designed self-defined security rule detection clause and the existing commercial clause, the present invention adds and realizes rule clauses such as FPGA state machine deadlock and internal tri-state in the custom security rule detection clause, and improves the quality of FPGA code ; Deletion of rules that do not apply to FPGA testability design, electrical characteristics testing and other rules, effectively reducing the terms of invalid warning rules.

Description

technical field [0001] The invention relates to the technical field of FPGA verification, in particular to a method for detecting safety rules of FPGA / IP core logic codes. Background technique [0002] In terms of verification of programmable devices, there are mainly methods such as simulation verification, formal verification, and static rule detection. When the verification method of simulation is used, the simulation speed of the simulator will decrease significantly with the increase of the design scale, and at the same time, the increased design scale will also increase the probability of errors in the simulation process of the software simulator. The same problem is faced when using formal methods. Due to the increase in design size, even the design at the module level becomes large in size, and the problem of state space explosion in formal methods makes formal inspection tools difficult to deal with Design time becomes powerless. Static rule detection method is th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/36
CPCG06F11/3604
Inventor 李东方王晓龙陈丽容胡亚云朱秋岩王宏王志昊沈炜王纪叶东升吴超张建伟宋珺
Owner BEIJING INST OF COMP TECH & APPL
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