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Wafer flatness control using back compensation structure

A technology for compensating structure and flatness, which is applied in the field of forming semiconductor structures and controlling wafer flatness, and can solve problems such as changing device feature patterns and die yield loss.

Inactive Publication Date: 2019-01-04
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, severe changes in surface topography within the exposed area can alter the device feature pattern and ultimately lead to potential die yield loss

Method used

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  • Wafer flatness control using back compensation structure
  • Wafer flatness control using back compensation structure
  • Wafer flatness control using back compensation structure

Examples

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Embodiment Construction

[0021] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in a variety of other applications.

[0022] It is noted that references in the specification to "one embodiment," "an embodiment," "exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but Not every embodiment may include that particular feature, structure or characteristic. Furthermore, such phrases are not necessarily referring to the same embodiment. In addition, when a particular feature, structure or characteristic is described in connection with an embodim...

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PUM

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Abstract

Embodiments of a semiconductor structure for wafer flatness control and a method for using and forming the semiconductor structure are disclosed. In an example, a model indicative of the flatness difference between the first direction and the second direction of the wafer is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of a wafer. A compensation pattern for reducing a flatness difference based on the model is determined. In one of the plurality of fabrication stages, a compensation structure is formed on the back surface of the wafer opposite to the front surface based on the compensation pattern so as to reduce the flatness difference.

Description

Background technique [0001] Embodiments of the present disclosure relate to wafer flatness control in semiconductor device fabrication. [0002] Wafer flatness has a significant impact on semiconductor device fabrication because it affects the ability of a lithography system to efficiently project device patterns. However, severe changes in surface topography within the exposed area may alter the device feature pattern and ultimately lead to potential die yield loss. Thus, for accurate projection, it is important to expose the pattern of light on a relatively flat or planar wafer. Wafer flatness is also important for other fabrication processes. For example, during the bonding process, the flatness of each wafer to be bonded must be controlled within reasonable tolerances to ensure direct contact between the two bonding surfaces. Contents of the invention [0003] Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the semi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/3205H01L27/11578H01L29/06H10B43/20
CPCH01L29/0657H01L21/02112H01L21/02164H01L21/0217H01L21/32055H10B43/20H01L21/2007H01L22/20H01L22/12H01L21/302G03F7/70783H10B43/27G03F7/70691H01L21/02016H01L21/02035H01L21/02274H01L21/02612H01L24/94
Inventor 戴晓望吕震宇陶谦胡禺石夏季李兆松何家兰
Owner YANGTZE MEMORY TECH CO LTD