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Negative boost circuit, semiconductor device and electronic device

A technology of negative boost and boost capacitor, which is applied in the direction of instruments, static memory, read-only memory, etc., can solve the problems affecting the performance of P-type multi-time programmable memory, and achieve the effect of reducing the gap

Active Publication Date: 2021-06-22
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The negative bias voltage is generally generated by a negative boost circuit, and the level of the bias voltage is affected by the operating voltage VCC, temperature and process variation (ie process angle), thus affecting the P-type multiple programmable ( MTP) memory performance

Method used

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  • Negative boost circuit, semiconductor device and electronic device
  • Negative boost circuit, semiconductor device and electronic device
  • Negative boost circuit, semiconductor device and electronic device

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Embodiment Construction

[0037] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0038] It should be understood that the invention can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and like reference numerals designate like elements throughout.

[0039] It will be understood that when an element or layer is referr...

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PUM

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Abstract

The invention provides a negative boost circuit, a semiconductor device and an electronic device. The negative boost circuit includes a main boost unit configured to generate a basic bias signal; a secondary boost unit configured to be connected in parallel with the main boost unit and configured to generate an additional bias signal to match the basic bias The negative bias voltage is formed by the voltage signal together; the voltage detector is configured to generate a voltage detection signal acting on the sub-boost unit based on the voltage of the output terminal of the negative boost circuit, and the voltage detection signal makes the sub-boost The unit generates the additional bias signal; wherein, the number of the sub-boosting units is greater than or equal to 2, and each of the sub-boosting units is correspondingly provided with the voltage detector. The negative boost circuit of the present invention can reduce the influence of VCC, temperature and process on the negative bias voltage, and narrow the gap of the negative bias voltage under various working conditions. The semiconductor device and electronic device of the present invention have better read operation performance.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a negative boost circuit, a semiconductor device and an electronic device. Background technique [0002] P-type multiple-time programmable (MTP) memory has multiple operations of programming, erasing and reading, and it requires a negative bias of -1.5*VCC during the reading operation. The negative bias voltage is generally generated by a negative boost circuit, and the level of the bias voltage is affected by the operating voltage VCC, temperature and process variation (ie process angle), thus affecting the P-type multiple programmable ( MTP) memory performance. [0003] Therefore, it is necessary to provide a negative boost circuit, a semiconductor device and an electronic device to at least partially solve the above problems. Contents of the invention [0004] A series of concepts in simplified form are introduced in the Summary of the Invention, which will be furth...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C5/14G11C16/30
CPCG11C5/147G11C16/30
Inventor 权彝振倪昊刘晓艳
Owner SEMICON MFG INT (SHANGHAI) CORP