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Power system on-off shift processing method based on FPGA

A technology of drive-in displacement and processing method, which is applied in the field of FPGA-based power system drive-in displacement processing, which can solve problems such as increasing difficulty in system accident analysis, affecting power system scheduling, and deviations in action time, etc., to achieve convenient simultaneous processing , Guarantee accuracy, improve the effect of resolution

Inactive Publication Date: 2019-03-01
INTEGRATED ELECTRONICS SYST LAB
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the input displacement event does not match the actual situation or deviates from the actual action time, it will directly affect the dispatching of the power system, and at the same time make it more difficult to analyze system accidents

Method used

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  • Power system on-off shift processing method based on FPGA

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Embodiment Construction

[0019] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Such as figure 1 Shown is a logic flow diagram of a FPGA-based power system input displacement processing method of the present invention, comprising the following steps:

[0020] Step 1. Obtain accurate time according to the time synchronization signal. The specific method is to use the FPGA internal time synchronization module to obtain accurate time according to the GPS time synchronization signal; FPGA includes a time synchronization module, a status reading module, a status comparison module, a timing module, and a continuous Confirmation module, event generation module.

[0021] Step 2. Read the current input state information through the FPGA state reading module and save it in the FPGA internal register.

[0022] Step 3. Judging whether the current input state is consistent with the last time through the FPGA state comparison module, if yes, re...

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Abstract

The invention relates to a power system on-off shift processing method based on an FPGA. The FPGA comprises a clock synchronization module, a state reading module, a state comparing module, a timing module, a continuous confirming module and an event generating module. Firstly, accurate time and current on-off state information are obtained; then debouncing time Td and confirming time Tc are set to remove on-off interference, on-off shift is accurately distinguished, no shift events are generated in the debouncing time and the confirming time, and when the confirming time is over, an on-off shift event is generated for an on-off state with stable shift, so that not only is resolution of on-off shift improved, but also the accuracy of time scales is guaranteed. The parallel processing characteristic of the FPGA is used, so that multipath on-off shift can be conveniently processed simultaneously, and the fact that the processing performance does not change along with change of the numberof on-off paths is guaranteed.

Description

technical field [0001] The invention belongs to the technical field of electric power system automation management, and in particular relates to an FPGA-based power system input displacement processing method. Background technique [0002] The input is an important data that reflects the operation status of the power equipment in the power system, and the input displacement event provides an objective basis for the analysis of the power system accident. If the drive-in displacement event does not match the actual situation or deviates from the actual action time, it will directly affect the dispatching of the power system, and at the same time make the analysis of system accidents more difficult. In an environment with a lot of interference, the state value of the input will change repeatedly. In this case, removing the interference of the input and accurately and quickly identifying the normal input displacement can effectively avoid false alarms and missed reports of the i...

Claims

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Application Information

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IPC IPC(8): G07C1/10G06Q50/06
CPCG06Q50/06G07C1/10
Inventor 李冰滕兆宏张亮曹敏赵胜王星维
Owner INTEGRATED ELECTRONICS SYST LAB