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An instruction processing method, a CPU interaction system and a consumable chip using the system

An interactive system and instruction processing technology, applied in the field of data processing, can solve problems such as information real-time processing needs to be improved, improve CPU system utilization and overall performance, meet high real-time performance requirements, and improve bus efficiency and CPU utilization. rate effect

Active Publication Date: 2021-03-19
HANGZHOU CHIPJET TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The existing consumable chip adopts the existing sequentially executed CPU system. Therefore, the real-time information processing of the consumable chip needs to be improved.

Method used

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  • An instruction processing method, a CPU interaction system and a consumable chip using the system
  • An instruction processing method, a CPU interaction system and a consumable chip using the system
  • An instruction processing method, a CPU interaction system and a consumable chip using the system

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Embodiment Construction

[0052] The following are specific embodiments of the present invention and in conjunction with the accompanying drawings, the technical solutions of the present invention are further described, but the present invention is not limited to these embodiments.

[0053] The CPU interaction system includes a master interaction module, a slave interaction module, and a task processing module. The main interaction module, the slave interaction module and the task processing module are connected to the bus, and the master interaction module respectively accesses the slave interaction module and the task processing module through the bus. During the access period, the CPU's instructions are executed sequentially, and there is an idle period between adjacent instructions during instruction execution, which is defined as an instruction gap in this paper. During the execution of instructions, these instruction gaps are often not used. If the main interaction module accesses the task proces...

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Abstract

The invention relates to an instruction processing method, a CPU interaction system and a consumable chip adopting the system, belonging to the technical field of data processing. The method is used for a CPU interaction system, and the CPU interaction system comprises a master interaction module, a slave interaction module and a task processing module connected to the bus. The CPU interaction system also includes a detection module. The method comprises the following steps: when the master interaction module accesses the slave interaction module, the detection module detects the instruction gap; The instruction gap is the idle period between adjacent instructions. The detecting module matches the task instructions executable by the main interactive module in the instruction gap, and feedsback the matched task instructions to the main interactive module. The main interactive module accesses the task processing module according to the task instruction fed back by the detection module.The consumable chip adopts the CPU interaction system. The invention fully utilizes the instruction gap to execute additional working instructions without affecting the execution process of common instructions, and improves bus efficiency and CPU utilization rate.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a CPU-based instruction processing method under MCU application, a CPU interactive system and a consumable chip using the system. Background technique [0002] All the current MCU application fields are all centered on the central processing unit (CPU), and the CPU is used as the main interactive module, and a series of operations such as calculation, operation, and control are performed through CPU machine instructions to access the slave interactive module. In the CPU interactive system composed of the master interactive module and the slave interactive module, the above-mentioned operations performed by the master interactive module, that is, the execution of CPU instructions, are executed sequentially. Even if the pipeline operation is added, it only increases the number of calculations in a single clock cycle, while the CPU instructions are still executed serially. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/50
CPCG06F9/3004G06F9/5027
Inventor 刘天翔
Owner HANGZHOU CHIPJET TECH CO LTD