A DSP multi-core parallel computing scheduling method based on inter-core interrupt
A technology of parallel computing and scheduling method, applied in the direction of computing, inter-program communication, multi-program device, etc., can solve the problems of data packet reception failure, lack of versatility, unable to realize the data flow model of the communication system, etc., to achieve high versatility Effect
Active Publication Date: 2021-03-30
SHANGHAI RES CENT FOR WIRELESS COMM
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If the data packet contains the control information in the communication protocol, it will also cause the next series of data packets to fail to receive
[0004] In addition, in the existing literature (such as reference [1] Yang Fang, Research on the application technology of multi-core DSP parallel processing based on TMS320C6678, master thesis of Beijing Institute of Technology, June 2014), for FFT (fast Fourier transform), Application scenarios such as radar imaging have developed special parallel processing mechanisms, but most of these parallel processing mechanisms have been customized for specific computing tasks and lack versatility, so it is difficult to directly apply them to other computing tasks
For example, the parallel mechanism in the above reference [1] is only suitable for the master-slave model, but cannot realize the data flow model required in the communication system
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[0060] The technical content of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0061] Such as figure 1 As shown, the DSP multi-core parallel computing scheduling method based on inter-core interrupt provided by the present invention comprises the following steps:
[0062] Step S1: According to the parallel computing model used, configure the inter-core relational data structure in the source code;
[0063] Step S2: configuring the buffer data structure in the source code for the forward buffer and the backward buffer in the inter-core relational data structure;
[0064] Step S3: compiling the source code into an executable binary file and downloading it to the DSP;
[0065] Step S4: DSP runs the program, wherein core 0 controls the start and end of each processing cycle through an inter-core interrupt, and processes some data; meanwhile, cores other than core 0 perform data processing ...
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The invention discloses a DSP multi-core parallel computing scheduling method based on inter-core interruption. The scheduling method comprises the following steps of configuring an inter-core relation data structure in a source code according to a used parallel computing model; configuring a buffer area data structure for a forward buffer area and a backward buffer area in the inter-core relationdata structure in the source code; compiling the source code into an executable binary file, and downloading the executable binary file into the DSP; using the DSP to runs a program, wherein the core0 controls the start and end of each processing period through inter-core interruption, and part of data is processed; at the same time, using the cores except the core 0 to carry out data processingaccording to an inter-core interruption period. According to the scheduling method, the multi-core parallel computing of the DSP can be realized under the condition of not using any operating system,and a plurality of parallel computing models are supported, so that the method has very high universality.
Description
technical field [0001] The invention relates to a DSP multi-core parallel computing scheduling method, in particular to a DSP multi-core parallel computing scheduling method based on inter-core interruption. Background technique [0002] In the DSP (Digital Signal Processor) field, the most popular multi-core parallel computing mechanism is the SYS / BIOS operating system of TI (Texas Instruments, USA). This operating system encapsulates the underlying hardware details, which greatly reduces the technical threshold for using multi-core DSP. In particular, TI has also transplanted the parallel computing application program interface OpenMP to the SYS / BIOS operating system, so that programmers can easily convert the original single-core running program into a multi-core parallel computing program. [0003] However, some application areas have strict requirements on the delay of processing data. If you use an operating system, it will be difficult to precisely control the delay...
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IPC IPC(8): G06F9/48G06F9/54
CPCG06F9/4812G06F9/4881G06F9/544G06F9/545
Inventor 王旭马慧舒睿俊徐景张武雄
Owner SHANGHAI RES CENT FOR WIRELESS COMM