K series fpga internal clb module positioning and general configuration test method

Abstract

The present invention provides K7 series FPGA internal CLB module positioning and universal configuration testing method, including: positioning the specific position of all CLB modules inside the FPGA; performing left and right equal divisions on the CLB module array, and in each equal division, the CLB modules of the same row are parallel, and the CLBs of the same column Modules are configured serially to achieve full coverage of CLB resources; the built-in self-test is performed on the configured CLB module array, and by comparing the actual output data with the expected data, it is judged whether there is a defect in the CLB module array. The problem is to locate the specific location of the CLB module error according to the corresponding relationship between the output signal and the clock. The K7 series FPGA internal CLB module positioning and universal configuration testing method provided by the present invention realizes the positioning of all CLB modules without calculating the specific position of the "hole" array, optimizes the configuration program, and realizes the optimal configuration times and configuration program It is versatile and reduces the time for repeated program writing.

Description

technical field [0001] The present invention relates to the technical field of FPGA testing, in particular to K7 series FPGA internal CLB module positioning and universal configuration testing methods. Background technique [0002] Kintex-7 series FPGA is a high-end FPGA product developed by Xilinx. It is widely used in 3G / 4G wireless, flat panel display, Video, aerospace systems, etc. FPGA is mainly composed of programmable logic unit (CLB), input and output unit (IOB), 90% of the logic resource functions in the FPGA are realized by the CLB module, so the CLB module test occupies an important position in the FPGA test. However, the CLB module array of the K7 series FPGA is different from Xilinx's previous Virtex4 and Virtex5 series FPGAs. Its distribution is asymmetrical and has "holes", which require precise positioning of the CLB module array. [0003] For the "hole" CLB array, the traditional configuration program has two methods, adopting an all-serial architecture or ...

AI Technical Summary

Problems solved by technology

[0005] The object of the present invention is to provide K7 series FPGA internal CLB module location and universality configuration test method, to solve the CLB array existence " cavity " is difficult to locate and configuration program design complexity, the poor problem of configuration program portability

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