Power supply protection clamping circuit module and clamping circuit

Abstract

The invention discloses a power supply protection clamping circuit module and a clamping circuit. In the clamping circuit module, a free end of a resistor is connected with an NET1; the resistor and acapacitor are connected with an input end of a phase inverter through an NET7; a source electrode and a substrate of a first NMOS (N-channel Metal Oxide Semiconductor) pipe of the phase inverter areconnected with a free end of the capacitor through an NET4; an output end of the phase inverter is connected with a grid electrode and a substrate of a second NMOS pipe through an NET5; a source electrode and a substrate of a PMOS (P-channel Metal Oxide Semiconductor) pipe of the phase inverter are connected with an NET2; a source electrode and a drain electrode of the second NMOS pipe are in buttjoint with an NET3 and an NET6 in a one-to-one correspondence manner; the clamping circuit comprises N clamping circuit modules; the NET1, the NET2 and the NET3 of the first clamping circuit module are connected with a power supply; the NET4, the NET5 and the NET6 of the former clamping circuit module are connected with the NET1, the NET2 and the NET3 of the latter clamping circuit module in a one-to-one correspondence manner; the NET4 and the NET6 of the Nth clamping circuit module are grounded. The power supply protection clamping circuit module disclosed by the invention can be used for protecting the power supply which is greater than normal working voltage of a device and the anti-ESD (Electro-Static Discharge) capability of a chip of the high-voltage power supply is ensured; the power supply protection clamping circuit module has no influence on normal work of the chip.

Description

technical field [0001] The invention relates to the technical field of double-gate process circuit design, in particular to a power supply protection clamping circuit module and a clamping circuit. Background technique [0002] In double-gate processes such as SOI (silicon on insulating substrate) technology, the substrate of MOS (metal oxide semiconductor) transistors can be applied with voltage to control the turn-on current of MOS devices, and the substrate is called the back gate. Due to the particularity of this type of process, ESD (electrostatic discharge) protection parasitic devices cannot exist in this type of process, and the ESD design of the chip is particularly important. The traditional ESD power supply protection clamp circuit design is usually RC-NMOS structure, such as figure 1 As shown, the power supply and the ground are connected through an NMOS (N-type metal oxide semiconductor), and the Vds (source-drain voltage) voltage difference that the NMOS can w...

AI Technical Summary

Problems solved by technology

The traditional ESD power supply protection clamp circuit design is usually RC-NMOS structure, such as figure 1 As shown, the power supply and the ground are connected through an NMOS (N-type metal oxide semiconductor), and the Vds (source-drain voltage) voltage difference that the NMOS can withstand when it is turned off cannot exceed the normal operating voltage of the device, so the The ESD power supply protection clamp circuit can only protect the power interface consistent with the normal working voltage of the device

At present, in some chip designs, it is necessary to protect the power interface that is greater than the normal operating voltage of the device, and the traditional ESD circuit structure is helpless.

Images