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Data access method and device based on multi-core processor

A multi-core processor and data technology, applied in the information field, can solve the problem of large storage space in the storage directory

Active Publication Date: 2021-06-01
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the implementation of this protocol, the directory needs to record the sharing of all data in the multi-core processor and the core corresponding to the copy of the shared data, resulting in a large storage space occupied by the storage directory.

Method used

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  • Data access method and device based on multi-core processor
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  • Data access method and device based on multi-core processor

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Embodiment Construction

[0040] The technical solution in this application will be described below with reference to the accompanying drawings.

[0041] For ease of understanding, first combine figure 1 The architecture of the multi-core processor in the embodiment of the present application is introduced. figure 1 The multi-core processor 100 shown includes multiple cores 110 , multiple L2 caches 120 , multiple hybrid cache management modules 130 , multiple coherency management modules 140 , L3 caches 150 and memory 160 .

[0042] The core 110 is used for executing instructions.

[0043] The L2 cache 120 (L2cache) is used to provide cache space for the core corresponding to the L2 cache. Each L2 cache is a private cache for the core, that is, the storage resources provided by the L2 cache can only be used by the core corresponding to the L2 cache.

[0044] figure 2 An architecture of a secondary cache is shown. figure 2 The illustrated L2 cache 120 may contain multiple cache sets (sets) 210, e...

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Abstract

Embodiments of the present application provide a multi-core processor-based data access method and device. The embodiment of the present application is based on the combination of two cache coherence protocols (directory-based cache coherence protocol and interception-based cache coherence protocol). First, the directory-based cache coherence protocol is used to maintain data consistency. For the data not recorded in the directory, the cache consistency protocol based on snooping is used to maintain the consistency of the data, so as to reduce the number of snoops sent through the bus.

Description

technical field [0001] The present application relates to the field of information technology, and more specifically, relates to a multi-core processor-based data access method and device. Background technique [0002] A multi-core processor refers to the integration of two or more complete computing engines (also known as "cores" or "cores") in one processor. Each core has its own secondary cache to store data or instructions. The L2 cache of each core belongs to the private cache of the core, that is, the cache space of the L2 cache is only provided for use by a specific core. However, the same data may exist in data used by different cores, that is to say, copies of the same data may be stored in L2 caches of different cores, and this data is called shared data. [0003] The presence of shared data introduces cache coherency issues. Currently, there are mainly two protocols for ensuring cache coherence: a cache coherence protocol based on snooping (or snooping protocol)...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/0897G06F12/0815
CPCG06F12/0815G06F12/0897
Inventor 宋昌
Owner HUAWEI TECH CO LTD