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A Current-fed Topological Voltage Stress Absorption Method

A technology of current feeding and voltage stress, applied in electrical components, adjusting electrical variables, converting DC power input to DC power output, etc., can solve the problem of leakage and source breakdown, reduce the Vds voltage, and solve the problem of over-specification. Effect

Active Publication Date: 2021-12-31
广东省洛仑兹技术股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The drain source of the switch tube will be broken down

Method used

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  • A Current-fed Topological Voltage Stress Absorption Method
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  • A Current-fed Topological Voltage Stress Absorption Method

Examples

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Embodiment 2

[0026] Embodiment 2: on the basis of embodiment 1, this method can also be applicable to such as Figure 4 The current-mode push-pull full-bridge bidirectional circuit shown can also reduce the Vds voltage of the switching tube and solve the problem of the Vds voltage exceeding the specification, and its principle is the same as that of Embodiment 1.

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Abstract

The invention discloses a method for absorbing current-fed topological voltage stress, which comprises the following steps: A. When the current of the inductor L is zero or at the bottom, the conduction time Δt of the switch tube S2 and the switch tube S3 is obtained by calculation or measurement ; B. When the system work is closed or the hiccup drive is closed, the switch tube S2 and the switch tube S3 are controlled to turn off the time by Δt time. The present invention adjusts the switch tube turn-off sequence so that the current of the inductor L is at zero or at the bottom, and the switch is turned off. Switch tubes S2, S3. In this way, the Vds voltage of the switching tube can be reduced, and the problem of the Vds voltage exceeding the specification can be solved.

Description

technical field [0001] The invention relates to the technical field of electric power, in particular to a method for absorbing current-fed topological voltage stress. Background technique [0002] figure 1 Current-fed bidirectional topology, switch tubes S1, S2, S3, and S4 form a full-bridge circuit to achieve, the circuit is as follows figure 1 as shown, figure 2 It is the signal waveform diagram added to the gates of the switch tubes S1, S2, S3, and S4. When the switch tubes S1 and S4 are turned off, and then S2 and S3 are turned off, because the inductance L still has energy, at this time, the energy of the inductance L passes through S2 and S3 The release of the parasitic junction capacitance of S2 and S3 causes the voltage stress at both ends of D and S of S2 and S3 to be very high, exceeding the specification of the switching tube. The drain-source of the switch tube will be broken down. [0003] The solution in the prior art is as follows: In the previous solutio...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02M1/32H02M3/335H02M3/337
Inventor 周建明
Owner 广东省洛仑兹技术股份有限公司