Integrated packaged semiconductor device

Abstract

The invention discloses an integrated packaged semiconductor device. The integrated packaged semiconductor device comprises: a signal transfer substrate, wherein the periphery of a bottom surface of the signal transfer substrate is provided with a chamfer; a package substrate, wherein the upper surface of the package substrate carries the signal transfer substrate; a chip, wherein the upper surface of the signal transfer substrate carries the chip; and first filling glue filling the position between the package substrate and the signal transfer substrate, wherein the difference in thermal expansion coefficient of the signal transfer substrate relative to the package substrate is greater than that of the signal transfer substrate relative to the chip. The periphery of the bottom surface ofthe signal transfer substrate is provided with the chamfer, namely, a sharp right angle which is easy to concentrate stress is cut or polished to form a chamfer, and the purpose is to disperse the stress to avoid cracking of the filled first filler due to too much stress so as to improve the yield of integrated packaged semiconductor devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to an integrated packaging semiconductor device. Background technique [0002] SIP (System In a Package) is a packaging process that integrates multiple functional chips, such as processors, memory and other functional chips, into one package to achieve a basically complete function. SIP is a packaging method in which different chips are placed side by side or stacked. The wiring on the packaging substrate is relatively wide, which can easily lead to wiring congestion. Therefore, there are great restrictions on the types of chips that can be realized and the number of chip connections. 2.5D packaging process. [0003] In 2.5D or 3D packaging, the purpose of setting the signal transfer substrate is to reduce the interface stress between the chip and the package substrate through the signal transfer substrate with matching thermal expansion coefficient. However, when ...

AI Technical Summary

Problems solved by technology

SIP is a packaging method in which different chips are placed side by side or stacked. The wiring on the packaging substrate is relatively wide, which can easily lead to wiring congestion. Therefore, there are great restrictions on the types of chips that can be realized and the number of chip connections. 2.5D packaging process

[0003] In 2.5D or 3D packaging, the purpose of setting the signal transfer substrate is to reduce the interface stress between the chip and the package substrate through the signal transfer substrate with matching thermal expansion coefficient. However, when the thermal stress is high, the sign

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