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Multi-chip wafer level package and method of forming the same

A wafer-level packaging and multi-chip technology, applied in semiconductor/solid-state device components, semiconductor devices, electrical components, etc.

Pending Publication Date: 2019-05-07
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there are many challenges associated with such multi-chip wafer-level packaging

Method used

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  • Multi-chip wafer level package and method of forming the same
  • Multi-chip wafer level package and method of forming the same
  • Multi-chip wafer level package and method of forming the same

Examples

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Embodiment Construction

[0012] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are set forth below for the purpose of conveying the disclosure in a simplified form. Of course, these are examples only and are not intended to be limiting. For example, the description below that a second feature is formed "on" a first feature or "on" a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which Embodiments in which an additional feature may be formed between a second feature and a first feature such that the second feature may not be in direct contact with the first feature. Additionally, the same reference numbers and / or letters may be used to refer to the same or similar components in various examples of the present disclosure. Reuse of reference numbers is f...

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Abstract

The embodiment of the invention provides a multi-chip wafer level package and a method of forming the same. The multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Description

technical field [0001] Embodiments of the present invention relate to a multi-chip wafer level package and a forming method thereof. Background technique [0002] In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density comes from successive reductions in minimum feature size, which enables more components to be integrated into a given area. [0003] These smaller electronic components also require smaller packages that occupy less area than previous packages. Examples of semiconductor package types include quad flat package (QFP), pin grid array (PGA) package, ball grid array (BGA) package, flip chip (flip chip, FC), three-dimensional Integrated circuit (three-dimensional integrated circuit, 3DIC), wafer level package (wafer level package, WLP), and package on p...

Claims

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Application Information

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IPC IPC(8): H01L25/16H01L23/31H01L21/98
CPCH01L23/3128H01L21/6835H01L2221/68345H01L2221/68359H01L23/5389H01L23/49816H01L21/486H01L23/49827H01L25/03H01L25/0652H01L2225/06517H01L2225/06548H01L2225/0652H01L25/50H01L2225/06572H01L2225/06541H01L2224/73267H01L2224/92244H01L2224/04105H01L2224/97H01L2224/81005H01L2224/12105H01L2224/11462H01L2224/11334H01L2224/131H01L2224/0401H01L2224/13082H01L2224/13147H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/92125H01L2924/15311H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2224/2518H01L2924/18162H01L2224/73259H01L2924/15192H01L24/19H01L2224/214H01L24/32H01L24/73H01L24/92H01L24/97H01L2224/81H01L2224/83H01L2924/014H01L2924/00014H01L2224/16225H01L2924/00H01L25/16H01L23/5383H01L21/568
Inventor 陈硕懋许峯诚黄翰祥刘献文郑心圃李孝文
Owner TAIWAN SEMICON MFG CO LTD