A scheduling system of a node controller and an FPGA board card

Abstract

The embodiment of the invention discloses a scheduling system of a node controller and an FPGA board card. Wherein the input channel of each connection port of the local node controller comprises a plurality of virtual channels used for caching corresponding type of message data, and the number of the virtual channels contained in the input channel is the same as the number of types of transmittedmessages; wherein each virtual channel has a cache with a preset depth and a credit value, the credit value serves as a standard for measuring the number of messages contained in the corresponding virtual channel, and the credit value changes along with the change of the number of the messages of the corresponding virtual channel; each remote node controller sends message data to the local node controller according to the credit value dynamically fed back by each virtual channel through the connection port; and each processing engine is used for scheduling the message data in the cache. The virtual channels are independent of one another and do not interfere with one another, so that congestion-free scheduling of interconnection of the node controllers and congestion-free scheduling of the routing layers of the node controllers are realized.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of distributed shared memory multiprocessors, in particular to a node controller scheduling system and an FPGA board. Background technique [0002] Cache-coherent distributed shared-memory multiprocessor system is an important system structure at present. At present, the processor is directly connected to the memory and supports the cache coherence protocol itself. Therefore, when building a multi-processor system, these processors are usually directly connected, and their own protocol maintains the consistency between the processors and forms a single Cache coherency domain. However, due to the limitations of protocol specifications, link ports, etc., the scale of such a single-domain multiprocessor system is usually limited. In order to realize a large-scale CC-NUMA (cache coherence Non Uniform Memory Access Architecture, consistent cache non-uniform memory access) multiprocessor sy...

AI Technical Summary

Problems solved by technology

[0005] The embodiment of the present disclosure provides a node controller scheduling system and an FPGA board, which solves the problem of congestion between channels when the node controllers are interconnected

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