A circuit for realizing sparse matrix multiplication and an FPGA board

A multiplication operation and sparse matrix technology, applied in the field of hardware design, can solve problems such as unsatisfactory real-time processing and low operation speed, and achieve the effect of improving efficiency and avoiding the calculation process

Inactive Publication Date: 2019-05-10
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a circuit and FPGA board for realizing sparse matrix multiplication, so as to solve the p

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  • A circuit for realizing sparse matrix multiplication and an FPGA board
  • A circuit for realizing sparse matrix multiplication and an FPGA board
  • A circuit for realizing sparse matrix multiplication and an FPGA board

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Embodiment Construction

[0033] The core of the present invention is to provide a circuit and FPGA board for realizing sparse matrix multiplication, which avoids the calculation process of a large number of zero elements and non-zero elements that do not need to participate in the operation, and significantly improves the efficiency of sparse matrix multiplication.

[0034] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0035] A kind of circuit embodiment one that realizes sparse matrix ...

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Abstract

The invention discloses a circuit for realizing sparse matrix multiplication. The circuit comprises multiple modules, all the modules are coordinated and matched; in the multiplication process of thesparse matrix, the sparse matrix can be multiplied; non-zero elements in the sparse matrix are screened out; in addition, the calculation process is carried out, column flag bits of all rows of a first matrix and row flag bits of all columns of a second matrix are subjected to bitwise operation; and finally, non-zero elements which really need to participate in operation are selected from the non-zero elements according to the target flag bit, so that the calculation process of a large number of zero elements and the non-zero elements which do not need to participate in operation is avoided,and the efficiency of sparse matrix multiplication operation is remarkably improved. In addition, the invention further provides an FPGA board, and the effect of the FPGA board corresponds to the effect of the circuit.

Description

technical field [0001] The invention relates to the field of hardware design, in particular to a circuit and an FPGA board for realizing sparse matrix multiplication. Background technique [0002] Sparse matrices are generated in almost all large-scale scientific and engineering computing fields, including popular fields such as machine learning, big data, and image processing. For a sparse matrix, the number of non-zero elements in the matrix is ​​much smaller than the total number of matrix elements, and the distribution of non-zero elements is irregular. If the sparse matrix is ​​calculated according to the conventional matrix calculation method, the storage space will be greatly wasted. It also greatly reduces the calculation speed. In some scenarios that have extremely high requirements on processing speed, if software processing is used, the processing speed is low and cannot meet the requirements of real-time processing. Contents of the invention [0003] The purp...

Claims

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Application Information

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IPC IPC(8): G06F17/16G06F15/78
Inventor 张贞雷
Owner ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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